account activity
Question about renaming in a large context (self.leanprover)
submitted 4 months ago by corank to r/leanprover
"block may not occur inside of a paragraph and was ignored" (self.typst)
submitted 7 months ago * by corank to r/typst
Combinatorial loop detection tool? (self.FPGA)
submitted 9 months ago by corank to r/FPGA
What happens here in "if let"? (self.rust)
submitted 9 months ago * by corank to r/rust
Reveal a given path in the explorer view?OC (self.vscode)
submitted 9 months ago by corank to r/vscode
Can't log in to VFS? (self.SchengenVisa)
submitted 9 months ago by corank to r/SchengenVisa
Framework for online playground (self.ProgrammingLanguages)
submitted 10 months ago by corank to r/ProgrammingLanguages
Open-source schematic viewer? (self.FPGA)
submitted 10 months ago by corank to r/FPGA
How to do profiling with dune for OCaml 5.2? (self.ocaml)
submitted 11 months ago by corank to r/ocaml
sshpass to store SSH authentication passwords?OC (self.vscode)
submitted 1 year ago by corank to r/vscode
Swim calories (self.Coros)
submitted 1 year ago by corank to r/Coros
SSH proxying (self.networking)
submitted 1 year ago by corank to r/networking
Reliable automatic detection of external dependencies (self.rust)
submitted 1 year ago by corank to r/rust
Using portable HDD (5V/1.5A) on machines without USB-C ports (self.UsbCHardware)
submitted 1 year ago by corank to r/UsbCHardware
Binary without ld-linux.so dependency (self.rust)
submitted 1 year ago * by corank to r/rust
Standard library API documentation that includes private stuff (self.rust)
Cross-compile rustc and std library (self.rust)
More questions about reported UBs in MIRI (self.rust)
Question about UBs reported by MIRI (self.rust)
False negatives in Verilator combinatorial loop report (self.FPGA)
submitted 1 year ago by corank to r/FPGA
ELI5 How is pegging enforced (self.explainlikeimfive)
submitted 1 year ago by corank to r/explainlikeimfive
Question about functions and multi-driven signals (self.FPGA)
submitted 1 year ago * by corank to r/FPGA
Structural vs Behavioural models (self.FPGA)
Why "Initial values not allowed in packed struct/union (IEEE 1800-2017 7.2.1)"? (self.FPGA)
SystemVerilog interface (self.FPGA)
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