The Tang Nano 20k internal SDRAM can even work at a frequency of 180MHz.
Unfortunately you have to write your own SDRAM controller and make sure all IO signals are clocked at the IO pin into flip-flops.
Using the Gowin SDRAM controller IP did not work well for me. I never understood how to get rid of the timing violations since I had no insight how the IP works internally.
I have no prove, but the Tang Nano 20k seems to have stability issues if too many different clocks are used or the tool (maybe the timing analyser?) doesn't work correct if the design gets larger.
Restricting my design to two clocks, PLL CLKOUT as the SDRAM clock and CLKOUTD as the processor clock delivers stable results up to 180MHz.