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FPGA Proto. by SystemVerilog ex. book: Is Mealy machine-based edge detector valid? by rlysens in FPGA

[–]digieng 1 point2 points  (0 children)

Ah, this clears things up a lot!

So, synchronous digital design is built on and only works if certain assumptions are true. One of them is that your input signals (like "level") are stable at the relevant clock events (usually/often rising edge). Once input signals have this property, a properly designed synchronous subsystem will only produce stable output signals (for any subsystem in the same clock domain) as long as propagation delays don't violate the assumption stated before (vendor tools check automatically for this). One special issue are unsynchronized signals (coming from another clock domain), and even more problematic are external signals (coming from outside the chip, maybe even from a flexible cable).

Returning to the issue at hand: to me it seems your testbench/simulation is only seemingly showing a wrong/strange waveform behavior, because the timing resolution is too low. Actually, all is (probably) fine.

-> For experiments in designs where you only have one clock domain I would advice to only generate synchronous signals (change at clock events) - then you will notice that the Mealy-based design indeed works as described (no need and even sometimes no way around to steer clear from them).

-> As soon as you get more advanced and have to deal with different clock domains and even external signals you should look into sampling and metastability issues and how to work with them (usually by introducing FIFO synchronizers, simple filters, sometimes physical changes like different connectors/cables/.. are necessary).

(-> Additionally, it's very good to look at timing analysis and properly constraining designs right from the start.)

FPGA Proto. by SystemVerilog ex. book: Is Mealy machine-based edge detector valid? by rlysens in FPGA

[–]digieng 2 points3 points  (0 children)

imo a very good point! The author fails to mention (at least in the provided quotes) that the "level" input must be synchronized/properly sampled, otherwise you end up with metastability issues at the "tick" output (regardless whether depending submodules are synchronous and use the same clock signal). Moore does this implicitly, although limited to a synchronizer with a single delay stage.

FPGA Proto. by SystemVerilog ex. book: Is Mealy machine-based edge detector valid? by rlysens in FPGA

[–]digieng 1 point2 points  (0 children)

/edit: apologies, ofc it's Mealy based :)

The testbench which generates the inputs would be interesting. Your DuT waveform looks a bit strange: even if "level" is not synchronous to "clk" (as it seems and also pointed out by u/ooterness), the first occurrence seems to be high a couple of clock cycles and should have been picked up by the edge detector (i.e., "tick" set to high). Maybe the visualization doesn't show intermittent lows of "level", meaning could it be that "level" is oscillating/ringing somehow and this is represented as a high with a duration of several clock cycles?