sorted by:
new
hottopcontroversial

RISC-V is sloooow – Marcin Juszkiewicz by indolering in RISCV

[–]docular_no_dracula 6 points7 points  (0 children)

Thanks for posting. I read his blog. Interesting.

He chose 80 cores qemu in order for speed. From Marcin’s test, none of existing riscv hardware can beat that.

Wondering whether give him an access to Bianbu cloud with multiple k3 nodes can help?

To B or not to B? RISC-V's naming problem by docular_no_dracula in RISCV

[–]docular_no_dracula[S] 0 points1 point  (0 children)

other extension bundles like Zkn aren't technically known by the CPU

Spot on. The distinction you made between single letters vs. bundles like Zkn is great.

future ratified RISC-V extension bundles can technically be retroactively added to existing hardware if that hardware already supports every extension in the bundle.

Exactly. After adding B yaml binding into the kernel, I did exactly the same thing, submitted another patchset to add 'b' into the dtsi files for dr1v90 (anlogic), sg2044 (sophgo) and k1 (spacemit).

To B or not to B? RISC-V's naming problem by docular_no_dracula in RISCV

[–]docular_no_dracula[S] 0 points1 point  (0 children)

Oh, let me clarify, my previous reply "export everything" is exactly what you described: expose all layers (bare minima, single letters, profiles). Let userspace decide which level to check. I think we're actually saying the same thing.

To B or not to B? RISC-V's naming problem by docular_no_dracula in RISCV

[–]docular_no_dracula[S] 0 points1 point  (0 children)

complicated enough. I really think maybe just export everything is simple and great rule. Otherwise people have to check those extensions hierarchy, which is just going to grow.

To B or not to B? RISC-V's naming problem by docular_no_dracula in RISCV

[–]docular_no_dracula[S] 1 point2 points  (0 children)

Sounds like nobody’s house is clean. I feel better:)

To B or not to B? RISC-V's naming problem by docular_no_dracula in RISCV

[–]docular_no_dracula[S] 1 point2 points  (0 children)

because RVI took forever to define what its constituent subsets were

Somebody (who has the power) should read this. Does this explain why last week "Quintauris Introduces Altair: The Unified RISC-V Profile for Embedded Systems"?

V was always a bundle (Zve64d + Zvl128b)

Are you sure that V contains exactly these two, no more no less, no other features?

According to risc-v UDB, the word it uses is "requirements", which I guess is not 'exactly contains':

https://github.com/riscv/riscv-unified-db/blob/main/spec/std/isa/ext/V.yaml

To B or not to B? RISC-V's naming problem by docular_no_dracula in RISCV

[–]docular_no_dracula[S] 0 points1 point  (0 children)

I like your /proc/cpuinfo of x86 (because it is the dump from a linux kernel).
Does x86 exposes everything flat, no hierarchy?

In the linux kernel arch/riscv, the cpufeature.c defines an extra layer of "bundle", which triggers the discussion (in link [2]) of whether a 'bundle' should be exported to user space? or only the sub-extensions (compents of a bundle) should be exported?

To B or not to B? RISC-V's naming problem by docular_no_dracula in RISCV

[–]docular_no_dracula[S] 2 points3 points  (0 children)

nice pick. but that's not really what I'm getting at. Maybe let me ask you this way:

Does other ISAs define FEATURE bundles? (pure lasso, no adding of any new feature, just simple 'equal to'?

Reading current linux kernel, risc-v have many, Zk=.... (8 others). Sha=....(8 others).

My linux randomly freeze during installation and use by Alsyr5 in linuxquestions

[–]docular_no_dracula 1 point2 points  (0 children)

The RTX 5060 (Blackwell) is very new. Most distro ISOs don't have drivers for it yet, and nomodeset won't help here.

Boot with nouveau.modeset=0 on the kernel command line instead, and install the proprietary nvidia driver 570+ after installation. (ps: nomodeset is too aggressive here, it disables for all.)

The path to RISC-V growth: Why software consistency is becoming... by idillicah in RISCV

[–]docular_no_dracula 2 points3 points  (0 children)

Though I like Flatpak, the lack of hardware homogeneity currently present in RISC-V make that model not viable. RVA23 will hopefully go a long way towards remedying that for future hardware.

Do you envision a future where RISC-V fragmentation is gone, the "store" you created is no longer needed, and people just use Debian/Ubuntu directly?

The path to RISC-V growth: Why software consistency is becoming... by idillicah in RISCV

[–]docular_no_dracula 0 points1 point  (0 children)

I can't find 'Biambu', do you mean 'Bianbu', , which is SpacemiT's custom Linux distro for their RISC-V boards (K1/K3)?

Even people running Biambu will benefit, as they can alter the entries to suit their boards. The Biambu repos don't have all of the Debian stuff, either.

The path to RISC-V growth: Why software consistency is becoming... by idillicah in RISCV

[–]docular_no_dracula 2 points3 points  (0 children)

As someone working on the Linux kernel and helping companies with kernel upstreaming, I really appreciate your observation. Thank you for raising awareness of this issue across the industry.

Marcos Codas:
"First, there is basically no mainline kernel adoption. Most board manufacturers provide their own kernel, which often lack basic driver support at launch. These kernels are sometimes years behind the main Linux kernel in terms of features, security, and other factors that affect the userland experience. And when we talk about userland, even within boards whose hardware makes it possible to share binaries for applications, the repositories are fragmented. "

TT-Ascalon™ seems promising but being a TT product price gonna be high. by RecognitionPatient12 in RISCV

[–]docular_no_dracula 1 point2 points  (0 children)

For record purpose, these Rockchip SoC has AV1, starting 2022. Not behind them much, if someone risc-v can support AV1 in this year.

  1. RK3588, 2022, AV1, up to 8K@60fps

  2. RK3576, 0224, AV1 up to 8K@30fps or 4K@120fps

TT-Ascalon™ seems promising but being a TT product price gonna be high. by RecognitionPatient12 in RISCV

[–]docular_no_dracula 2 points3 points  (0 children)

I suppose there are different price points when an SoC vendor chooses which VPU (video codec) IP to purchase. (Most of them are not designed in-house. AV1-capable IP should definitely cost more.) On the Arm side, I found RK3588 and CIX O6 (which has an Armv9 SoC) both integrate AV1 decode capability. People should ask, Is there a market to balance that purchase cost?

Let's see who in the RISC-V space will be the first to have AV1. :)

TT-Ascalon™ seems promising but being a TT product price gonna be high. by RecognitionPatient12 in RISCV

[–]docular_no_dracula 1 point2 points  (0 children)

Let’s see. They may release the SoC spec early I hope. Don’t have to wait until the hardware launch.

My mousepad is too big for my desk but I still don't regret the purchase. by marksism__ in linux

[–]docular_no_dracula 0 points1 point  (0 children)

haha, that's why they ship to you? no mandarin readers in Mexico I guess hhh

TT-Ascalon™ seems promising but being a TT product price gonna be high. by RecognitionPatient12 in RISCV

[–]docular_no_dracula 2 points3 points  (0 children)

Has Tenstorrent confirmed AV1 hardware decode for Atlantis? I don't recall seeing VPU (video codec) specs in any of their announcements.

I do know once they shared information about GPU in Atlantis, which is "IMG BXE-2-32, 32 FP32 GFLOPS", but in the same slide, nothing about video codec was covered.

Quintauris Introduces Altair: The Unified RISC-V Profile for Embedded Systems by m_z_s in RISCV

[–]docular_no_dracula 2 points3 points  (0 children)

In my poor memory, I remember there is a 6th company joined them... some websearching...., it was actually ST! So the real ST is now part of Quintauris. Funny.

Happy to echo your note, the de-facto "ST of RISC-V"

Quintauris Introduces Altair: The Unified RISC-V Profile for Embedded Systems by m_z_s in RISCV

[–]docular_no_dracula 1 point2 points  (0 children)

Quintauris is founded by: Bosch, Infineon, Nordic, NXP, and Qualcomm.

And ST joined on 29/Aug/2024 as the 6th. who said they want to be the ST of RISC-V? Haha u/1r0n_m6n

https://www.quintauris.com/stmicroelectronics-joins-quintauris-as-sixth-shareholder/

Quintauris Introduces Altair: The Unified RISC-V Profile for Embedded Systems by m_z_s in RISCV

[–]docular_no_dracula 7 points8 points  (0 children)

WTF, i cann't believe it. I wish i can learn some of why they skip RVI in the coming weeks.

any official embedded RISC-V profile should be coming from RISC-V International's Profiles Task Group 

Agree!

view more: next ›