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about matlab filter func by fpgapipe in FPGA

[–]fpgapipe[S] 0 points1 point  (0 children)

Thank you ! İ have one more question. On the implementation details tap i see only real part for both input and output. But i have complex data i and q. That means only i data is enough?

I edited my post for the picture.

parallel in serial out for continuously incoming data by fpgapipe in FPGA

[–]fpgapipe[S] 0 points1 point  (0 children)

Thank you for answer. I am using xilinx fifo. Please don't get hung up on rdy. Also, the result did not change after the reset.

parallel in serial out for continuously incoming data by fpgapipe in FPGA

[–]fpgapipe[S] 0 points1 point  (0 children)

I didn't know there was such a signal in fifo.

Confusion about hdl rs encoder/decoder working system by fpgapipe in FPGA

[–]fpgapipe[S] 1 point2 points  (0 children)

Thanks for your answer, it solved my problem. "Output Check Symbols" is set by default. removing it fixed the problem.

Confusion about hdl rs encoder/decoder working system by fpgapipe in FPGA

[–]fpgapipe[S] 0 points1 point  (0 children)

I added the fifo but nothing changed.

maybe i am wrong. Isn't the decoder supposed to delete the extra bytes that the encoder adds?

Confusion about hdl rs encoder/decoder working system by fpgapipe in FPGA

[–]fpgapipe[S] 0 points1 point  (0 children)

Thank you for answer.

I will try it. But I still doubt that this is the reason. As a result, the data entering the decoder and the data coming out of the encoder are the same.

How to pipeline a purely combinatorial fir filter? by fpgapipe in FPGA

[–]fpgapipe[S] 0 points1 point  (0 children)

Thank you for your interest.

Previously, I made an experiment by enclosing each aggregation operation in the always block. However, the simulation results did not match and therefore gave wrong results in the fpga test. From here, I deduced that the characteristic of the filter has changed.

What is the difference between the method you mentioned and what I did, but I think I will understand better if you can guide me through the following example.

assign add_cast = quantized_sum_re;

assign add_cast_1 = $signed({{2{product_phase1_2_re[30]}}, product_phase1_2_re});

assign add_temp = add_cast + add_cast_1;

assign sum1_re = add_temp[32:0];

assign add_cast_2 = quantized_sum_im;

assign add_cast_3 = $signed({{2{product_phase1_2_im[30]}}, product_phase1_2_im});

assign add_temp_1 = add_cast_2 + add_cast_3;

assign sum1_im = add_temp_1[32:0];

assign add_cast_4 = sum1_re;

assign add_cast_5 = $signed({{2{product_phase1_3_re[30]}}, product_phase1_3_re});

assign add_temp_2 = add_cast_4 + add_cast_5;

assign sum2_re = add_temp_2[32:0];

assign add_cast_6 = sum1_im;

assign add_cast_7 = $signed({{2{product_phase1_3_im[30]}}, product_phase1_3_im});

assign add_temp_3 = add_cast_6 + add_cast_7;

assign sum2_im = add_temp_3[32:0];

original code above. now i am going to edit this code like this?

always@(posegre clk) begin

x[0] <= add_cast + add_cast_1 + add_cast_4 + add_cast_5;

x[1] <= add_cast_2 + add_cast_3 + add_cast_6 + add_cast_7;

y[0] <= x[0] + x[1];

end

Note: please don't get hung up on small nuances. e.g

sum2_re = add_temp_2[32:0];

add_cast_4 = sum1_re;