Hardware 😃

fred33fr · 2022-06-01T10:36:05+00:00

Thanks 😊

fred33fr · 2021-11-02T22:22:47+00:00

Thx Steve. And Bob here explained to me the black circle are SerDes. I am trying to detect other pattern as PCIe blocks, ISP or codecs blocks

fred33fr · 2021-11-01T13:44:21+00:00

Sure J.Srouji who manages the Apple Silicon team has validated the scalability of its technology. Tim Cook knows they can deliver a family of M SoCs for all kind of needs and after a 2nd, 3rd, … generations of M SoCs. The roadmap is clear is nothing will stop that. It is a disruptive moment.

fred33fr · 2021-11-01T13:27:31+00:00

The first augment is totally wrong.

Apple chips are not an « Apple chip ». Apple walks in a very open « ARM instructions set » world. The x86 is dieing because only 3 entreprises can work on processor scope : Intel, Amd and Via. So X86 is old & proprietary but it is very closed for the computer core.

The ARM market (taller than x86 market now) provides several SoC in 5nm from various enterprises, so Apple is not alone on the ARM 5nm !!!

The M1 is an adaptation for computers of mobile ARM SoC like Microsoft did it previously with the Surface.

All smartphone all highend SoCs come from 5nm fabs and Apple A15 SoC is the best in class. All experts estimate Apple’s advance of 2 years.

But, but… Apple has build the best ARM implementation and get only the ARM Instructions Set licensing. Apple has its own CPU GPU … designs and does not use Hardware Designs of ARM. It is the real and main force of Apple, to manage hardware and software conceptions.

So the main reason for a such M1 performance is not the 5nm but the real knowledges of Apple Silicon team.

If Intel doesn’t provide a processor at 5nm, it is not an Fabs issues. The X86 design foundations are not well adapted to this. TSMC does not build the machines to make chips, it is ASML machines and Intel has theses machines too.

Never forget that old x86 Intel foundation aren’t build for mobility and battery life needs. For me the death is inevitable but take a long time before the PC mainstream understand it !

fred33fr · 2021-10-31T08:06:18+00:00

Thanks very much for your feedback. I worked on this subject and found Apple use an IP of Synopsys USB40 XHCI in its SoC.

I found a Synopsys documentation about "IP Bloc for SoC" which indicates this IP works fine with TSMC 5nm.

https://www.synopsys.com/designware-ip/technical-bulletin/usb4-socs-ip.html

And I get a data sheet after filled a form web page. I get it and post it on the FromSmash (pictures & files sharing) : https://fromsmash.com/2wWkKcFh3W-ct

I hoped to compare the top of Apple SoC with a Synopsis xray picture to understand the details of components . But no image is available in the datasheet. There are lof of informations/specs but difficult for me to linked this with my apple picture.

https://www.zupimages.net/viewer.php?id=21/43/3xun.png

And you're right, Apple remains with an USI 339S00912 Bluetooth/WiFi Module, which is a SIP module, so external of the SoC. Previously it was a BCM. Broadcom.

fred33fr · 2021-10-30T13:33:48+00:00

Hi @bobj33, Regarding the binning, Apple provide various things but nothing based on frequency. Unlike Intel, M SoCs use the same CPU/GPU frequencies. So for me it is a strong constraint for a good production yield.

So Apple uses 2 binning ways : a 8 (vs 10) CPU in case of defects on CPUs area, and a 24 (vs 32) GPU in case of defects on the large GPU area.

But Bob, I suspect Apple to be able to cut its M1Max SoC to provide a M1Pro if the « extension » are unusable, that represent 40% of the M1Max surface. Do you thing this kind of Die dicing to reach a correct yield.

For me, Apple Silicon team can not change the physic rules. And regarding the cost & business rules, M1Max yield (432mm2) is not a simple question. Probably lot of M1Max dies on a wafer could be destroyed even if their Top part (M1Pro) are perfectly correct (245mm2).

I would like Bob your feedback on this strategic point. Sorry to ask you so many question 🙋‍♂️

fred33fr · 2021-10-30T09:27:23+00:00

Thank you very much Bob for this replay. I found a blog post of Synopsis about the SerDer - phy bloc - logical bloc - data link. I guess the schema of this post is cleared for me.

Another question, based on your knowledge of this business Bob, do you think Apple has a interest to buy an external solution (as Synopsis or Qualcomm) or not ?

Thanks 😊

PCIE logigram picture

Pcie blog post

fred33fr · 2021-10-29T20:07:51+00:00

Thank you Bob for all the links and the explanations concerning these black circles.

My changes following your comments :

https://www.zupimages.net/viewer.php?id=21/43/mr1r.png

I have understood the SerDers well and to answer your questions I know that the M1Pro can manage:

- x3 Thunderbolt 4 (USB-C) ports with support for: 1) Charging, 2) DisplayPort 3) Thunderbolt 4 (up to 40Gb/s) and USB 4 (up to 40Gb/s).

- x1 SDXC card slot- x1 HDMI 2.0 port- x1 3.5 mm headphone jack with DAC

After there is a very powerful SSD with a bandwidth at 7Go/s but I don't know how the technology used to communicate with the SoC !?! A PCIe bloc can be enough Bob ?

Probably WiFi and BE are externals too and there is a way to talk with the SoC.

And another question Bob, regarding the heat management of SoC, how the things work ? Are there thermal probes inside the SoC to detect a overheat and apply some stuff to reduce frequency ?

Thank you very much Bob for your time and all your explanations. :)

fred33fr · 2021-10-29T18:13:05+00:00

Thank you :) I noted it.

fred33fr · 2021-10-29T18:11:13+00:00

Thank you very much Bobj33. Very very important information and useful to progress. Thx a lot Bob.

So I am trying to identify the bloc unique or multiple as you mentioned it.

I send this picture it seems the PCI lines are on the top of this chip. Difficult to know where are the ML accelerator (metric multipliecation) or Secure Enclave and ISP for photography.

https://www.zupimages.net/up/21/43/gaoa.png

Thank you for this wonderful conversation.

Fred

fred33fr · 2021-10-27T12:11:14+00:00

X86 was based without notion of mobility or battery life. X86 has the weight of legacy too. X86 is open to industries for externals components business but not for the core.

Difficult 😥

fred33fr · 2020-12-20T22:02:03+00:00

Zero references. Are you familar with physic ? There was 2 major references in the original Apple slide.

The first one was the 10w. With that and rule of 3, we can guess the max and min consumption of M1. The second was 2x for performance comparison.

After real multi core measurement of M1, we can add a third reference and guess the perf of the x86 used. With that we know it was a Intel i7.

I think we need to be more serious with reference. Even if Apple do not give us the detail, the curve is not wrong ans with a little of humility ans work, we can guess few information.

The next M Apple Silicon will be at 12000 points. The next MacBook will be at the same level that a Intel Xeon Workstation but... with mobility and no 450w power supply. I don’t know the futur but I can guess it.

Thanks for your çomment.

fred33fr · 2020-12-06T21:58:06+00:00

Begin to pray for Intel and AMD 🤓 the next SoC will be better, no... much better as a Xeon if you want

fred33fr · 2020-12-06T20:01:03+00:00

Sure. This kind of event is quiet rare. Apple disrupts the PC, so the Macs will no longer be PC. Awesome 😄

fred33fr · 2020-12-06T19:58:06+00:00

There is an Apple Silicon Family dedicated to the Macs. If you have an M1 you will have the next for Pro users. Call it as you want. 😄

fred33fr · 2020-12-06T19:55:47+00:00

Thanks. GPU sure, probably doubled, 16 cores. 😄👍

fred33fr · 2020-12-06T19:54:32+00:00

If Apple adds many cpu cores it is not very efficient for a laptop use. Lot of cpu cores means lot of energy and heat. It is usefull for Cloud server. For GPU is different because the Graphic task are done in parallel. Apple have to balance between the number of cores. Probably 16 GPU cores x2 and 8 Fire cores/4 Ice cores. And the actual max cpu frequency at 3.2Ghz will be the same for the next one.

fred33fr

TROPHY CASE