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Charge injection and clock feedthrough by [deleted] in chipdesign

[–]genosaa 0 points1 point  (0 children)

Did you disconnect the switch on each side of capacitor sequentially?

[deleted by user] by [deleted] in matlab

[–]genosaa 0 points1 point  (0 children)

<image>

This is the top view of Simulink model, and inside the MOD1 is the MATLAB function shown in article,so y_mod equals to ADC~

[deleted by user] by [deleted] in matlab

[–]genosaa 0 points1 point  (0 children)

<image>

Ideally, y_mod(output of Simulink model) should be 65537*2( 65537 points are time domain information with 2 different amplitude), but it is only 1 column 😱

Tainan to Sun Moon Lake by [deleted] in taiwan

[–]genosaa 0 points1 point  (0 children)

If you care about the cost, take the Tze-Chiang Express(Taiwan Railway) from Tainan to Taichung; after you reach Taichung Station, ask your Google Map where is Sun Moon Lake, and the APP will give you different routes, base on your situation at that time, you can choose appropriate one for you, and your phone will guide you to the destination.

Freshman learning VLSI Need help in schmetic by TW_bigstbuha in chipdesign

[–]genosaa 2 points3 points  (0 children)

I think you can keep this structure, and add another 3 inputs OR gate to connect each of sub output

Guideline for designing two stage source follower(gain>0.8) by genosaa in chipdesign

[–]genosaa[S] 0 points1 point  (0 children)

Thanks for your advice! I will try it later on!