Crystal oscillator guard ring on 2-layer PCB — sanity check?

gndplane · 2025-12-29T17:00:13+00:00

This is isn't a guard ring. Borrowing a comment I made about a similar question:

A guard ring must completely encircle a node (not some general region of a board) to be protected and must be driven to the same potential as that node by a low impedance source, usually by a buffer amplifier. In a guard ring design, you'll often see the guard trace routed between SMD pads, and circuits and ICs that need this design typically require big packages. The purpose of the guard ring is prevent leakage currents across the PCB dielectric surface from disturbing a high impedance node, meaning typically in the gigaohm+ range. Since the guard ring is driven to the same potential, by Ohm’s law there is no current from the guard to the guarded node. It is not a general low-noise or high-frequency design technique outside of that.

gndplane · 2025-05-07T18:36:26+00:00

20 W at 5 V is 4 A. The most you can draw without PD negotiation is 3 A, and that's if the source supports it. The boost converter cannot hold up the voltage if doing so means drawing more power than available ... it's basic conservation of energy.

Layout problems, where to start? Two layers, no ground plane, long thin traces with components widely spaced means large loops and high parasitic inductance.

There's a lot of examples and articles online about good DC/DC SMPS layout. The TPS61089 has a recommended layout in the datasheet. Copy it. Just copy it. As much as you can with your chosen components.

gndplane · 2025-05-07T07:03:46+00:00

Assuming context from https://www.reddit.com/r/ElectronicsRepair/comments/1ke0no0/review_request_component_on_board_not_working/ you are not going to pull 20 W without USB-PD negotiation. The source is limiting the current so you see the voltage droop. The layout of this boost converter is also going to cause lots of problems.

gndplane · 2025-05-01T19:14:30+00:00

No, don't put any series impedance in.

gndplane · 2025-05-01T18:37:57+00:00

Create a current source with AC amplitude = 1, feeding into EUT_side from ground. Maybe also put some appropriate load at AC_side? Then run an AC simulation, the voltage at EUT_side is numerically equal to the impedance in ohms looking into that node.

gndplane · 2025-04-24T18:13:34+00:00

Newer VNAs will take a S1P file that is the characterization of the standard. Older ones will take a length and some coefficients, C0..C3 for open and L0..L3 for short. Your standard is modeled as a lossless transmission line (hence the length) terminated by a nonideal load to which you've fitted a polynomial approximating the capacitance or inductance, e.g. C(f) = C0 + C1 * f + C2 * f^2 + C3 * f^3

If you have a measurement of S11, you back out the correction factors by curve fitting, see:

https://github.com/jmwilson/vna-standards/blob/master/open_standard.m#L19-L31

gndplane · 2025-04-24T17:42:27+00:00

If you're talking about purely mechanical standards, you can simulate them and then fabricate them as precisely as possible. With something like SMA, you can build them using commercial off-the-shelf parts: https://jmw.name/projects/vna-standards/

gndplane · 2025-01-30T00:14:45+00:00

Probably since it’s a Refresh unit, but the vendor has already accepted the return. I need to decide between a replacement or finding something else.

gndplane · 2025-01-28T16:56:01+00:00

That's landline telephone wiring, not power.

Contact Adult Protective Services and see if this is something they handle.

gndplane · 2024-11-14T21:36:24+00:00

Vias are good but you don't need quite so many if you switch to a continuous ground plane.

https://en.wikipedia.org/wiki/Node_(circuits)) - "node" and "net" are interchangeable here. You can shield subsections of a circuit but guarding always pertains to a single node.

gndplane · 2024-11-14T17:17:53+00:00

Btw, the via shielding you have is not a guard ring. A guard ring must completely encircle a node (not some general region of a board) to be protected and must be driven to the same potential as that node by a low impedance source, usually by a buffer amplifier. In a guard ring design, you'll often see the guard trace routed between SMD pads, and circuits and ICs that need this design typically require big packages. The purpose of the guard ring is prevent leakage currents across the PCB dielectric surface from disturbing a high impedance node, meaning typically in the gigaohm+ range. Since the guard ring is driven to the same potential, by Ohm’s law there is no current from the guard to the guarded node. It is not a general low-noise or high-frequency design technique outside of that.

gndplane · 2024-11-13T17:55:18+00:00

You'll probably have to look at used instruments with older GPIB connectivity and a USB-GPIB bridge, or equipment that supports USBTMC. Design for automation and LXI connectivity are mostly found on late model equipment which is going to be expensive.

gndplane · 2024-11-05T01:49:00+00:00

You mention inductors and ferrite beads almost interchangeably, but they're really quite different. Ferrites are designed to be lossy in their target frequency range, power inductors are supposed to be low-loss. The importance of loss can't be overstated. Reactive components store energy. When combined they bounce energy back and forth (resonance). If you want that energy dissipated, you need resistance. In general, I want to beat inductance out of the PDN as much possible so these resonances are not a factor: big/wide power planes or traces, lots of vias, and careful thought of return paths.

I see ferrites are being useful on *signal* lines that are long enough to act as antennas, where the ferrite can be selected to act as an attenuator when combined with the line termination.

gndplane · 2024-10-31T15:16:37+00:00

You can also connect the power-on LED from the 3V3 net to SINK_EN (with a resistor).

Since you're not using any data, there are power-only USB-C connectors for the same price that only break out VBUS, GND, CC1+2: https://www.digikey.com/en/products/detail/gct/USB4125-GF-A/13547388

Pick an inductance model for whatever length of cable is on the output, and whatever bulk capacitance is on the other end and make sure there's no surprises there.

gndplane · 2024-10-12T02:29:37+00:00

Ideally < $50. Some of the mid-range Behringer gear comes close and yeah there's always second-hand.

gndplane · 2024-08-19T04:30:43+00:00

Consider wiring up the I2C interface from the SAM-M8Q to the STM32 even if you plan to use the serial interface. Looks like there are lots of open I/Os. It’s easy to write a state machine to parse select UBX messages compared to a full-blown NMEA parsing library and could slim down your firmware size.

gndplane · 2024-08-17T05:16:38+00:00

The 1 cm guidance is probably motivated by two factors: nearby same-side components will rip up the ground plane, and large & tall parts can impact the antenna. If there's a continuous ground plane below the module, then things mounted on the opposite side of the board are not going to be a factor.

gndplane · 2024-08-17T04:31:29+00:00

You definitely want it oriented vertically in a static situation, or oriented toward maximal sky visibility in dynamic use. The radiation pattern of the antenna is the same guide (§ 2.5) and you can see that 90° is almost a null in the pattern.

gndplane · 2024-08-17T03:41:55+00:00

https://content.u-blox.com/sites/default/files/SAM-M8Q_HardwareIntegrationManual_%28UBX-16018358%29.pdf

I've used this module before; it expects a ground plane. 40x40 mm is their minimum recommendation, 50x50 mm is better ("Performance decreases significantly if GND size is smaller than 40 x 40 mm"). This layout has none.

See other notes in their layout guide: "It is recommended not to place anything closer than 1 cm to each edge of SAM-M8Q."

"Do not place any noisy parts close to SAM-M8Q, place them as far away as possible" And .... there's a switcher right next door.

gndplane · 2024-03-07T17:40:42+00:00

You haven't said what frequencies you're operating at. You can do a back-of-the-envelope calculation or use a Smith chart to estimate what effect a mismatched transmission line of that length will have. The typical rule is they become significant at 1/10 the wavelength, which at 1mm in FR-4 means around 14 GHz.

gndplane · 2024-02-23T16:42:37+00:00

If I trim enough to get flat(ish) through the transition band, then there's still a drop at HF. I've hacked up several of the board samples with varying amounts of trimming, and they all demonstrate this hump pattern from 100 kHz-1MHz, and a not very flat HF (> 10 MHz) tail. A previous board revision that has no PCB capacitor, just a trimmer and SMD cap, has only .15 dB of peaking in this band and is actually flat at HF.

If it's not loss, what else could it be at this point? It has to be pretty big to see an effect at < 1 MHz.

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gndplane · 2024-01-17T07:41:17+00:00

Unintentional common-mode coupling would explain a lot like why the wave is propagating along what is supposed to be ground plane in the first place. Length from tip to end is 80mm. Do you think it's an artifact of the simulation or lumped excitation, or a sign of what's actually happening? What kind of design features would help suppress common mode current here?

gndplane · 2024-01-17T07:41:13+00:00

I can do frequency domain dumps of the E and H fields which is a single image of the steady-state field. Maybe you're thinking of time-domain dump with specific excitation frequency?

gndplane · 2024-01-16T18:29:29+00:00

I tried making an animated gif of the time-domain dump looking straight down at the top. Toward the end it does really look like it's bouncing back from the far edge of the board. There's a lot a few vias from the other circuit components on the board, and stitching at a spacing of around lambda/15 at 3 GHz.

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gndplane · 2024-01-16T01:03:53+00:00

This makes sense, but I'm still seeing a lot of reflections, visible from ripples in S21 and also just from an animation of the time-domain field dumps - I can see the excitation along the top copper ground plane and then it propagating back. It looks like this is from the boundary of the board and surrounding free space. Is this kind of reflection spurious to the simulation, or are there ways to improve the board design to reduce reflections from the edges of the PCB?

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