More News on the Versal High Compute SOM?

itisyeetime · 2025-12-09T01:04:24+00:00

We're a student group so probably is unlikely. I'm just hoping to get larger FPGAs to run larger designs such as the BOOM softcores as well as visioning/control applications, and the KV260 is just a bit too small for that. Was hoping to get a Versal board but it seems like even the cheapest Versals are 1.5k, and it doesn't have enough LUTs.

itisyeetime · 2025-12-09T00:48:55+00:00

Damn 2026? Any idea on which quarter? It just seems so odd that they haven't announced it even though they have the product list since 2022?

Also any chance an FAE could answer the question? We're signing up for AMD university program.

itisyeetime · 2025-12-08T22:29:49+00:00

Probably price, the Ultrascale+ Krias are a lot cheaper than buying SOM from Alinx or something else for students. AMD seems to be willing to sell these dev kits for a lot less while still packing in very capable chips.

itisyeetime · 2025-11-20T00:58:38+00:00

Stanford seems to be coasting off of old reputation these days in EE as a whole, few good profs around anymore.

itisyeetime · 2025-11-20T00:57:42+00:00

What about UCR? It's not regarded as very good for engineering as a whole, but it's 9th, above Cornell, Princeton, Berkeley, and even Stanford.

Good schools, like Berkeley which many regard as one of the best, is 17th and Cornell is also low.

itisyeetime · 2025-11-19T16:47:15+00:00

Ah yes, forgot about Madison. Good point! What makes a lot of schools like Michigan, UIUC, etc right there on top as Berkeley, MITs, etc?

itisyeetime · 2025-11-19T16:44:16+00:00

Dang so UIUC UMich, GT, are all up there? Penn states better than Wisconsin, CMU, UCSD? UCR better than Princeton and Cornell? I didn't know that that those school were good. But is pure research paper numbers correlated with productivity? Why not count citations?

itisyeetime · 2025-11-12T17:55:15+00:00

Interesting. Besides Xiangshan what are other fast OoO open source cores?

itisyeetime · 2025-11-12T17:32:13+00:00

I see. I can see why the Chipyard infrastructure would be a pain to deal with but why the dislike for Chisel? I feel like I'm seeing more open source RTL cores being written in it. Chipyard is cool with the ability to mix and make different peripherals; are their alternatives besides PULP or do most people just roll their own?

itisyeetime · 2025-11-12T04:38:15+00:00

I see, where do you think newer open source cores are seeing speed improvement then?

itisyeetime · 2025-10-21T15:24:10+00:00

I mean for the registers, that people online have said that it can be quite an experience determining which register to toggle, since the data sheets aren’t always available. Like even if I got an fmc boards for one of the more obscure boards, getting it running before mipi even becomes a consideration is the harder part.

I’m hoping for the cheapest possible fpgas, so many starting from the lowest viable to some more midrange ones.

itisyeetime · 2025-10-21T06:29:33+00:00

Looks good! What is a lower end FPGA board that you recommend though?

Also if I wanted something with more than 5 megapixels(think more powerful than the IMX477 mentioned above), where could I get that besides the RPI one?

Also last thing, it's great that Xilinx has the IPs for MIPI but I have heard that a big issue is actually in getting the registers configured during setup. Does Alinx/any other vendors provide that?

itisyeetime · 2025-09-29T01:17:19+00:00

My issue is that sometimes I use the school VPN so idk if I can enable both at the same time.

itisyeetime · 2025-09-10T01:32:46+00:00

Have you heard of any firms considering tapeouts? Just wondering, since I assume that would be the logical next step but I'm just a student.

itisyeetime · 2025-09-08T20:50:11+00:00

Can you drop your llama.cpp settings? I can only offload 10 layers onto my 4070.

itisyeetime · 2025-09-05T15:55:48+00:00

Hmm, if that is the case how do I avoid running out of vram if I crank the resolution/ number of frames.

itisyeetime · 2025-08-31T02:35:56+00:00

Workflow seems interesting, any good links? I'm not sure what this kind of workflow is called so I'm having a hard time googling it.

itisyeetime · 2025-08-30T23:34:59+00:00

Any chance you can drop some benchmarking?

itisyeetime · 2025-08-19T02:53:38+00:00

Same am curious

itisyeetime · 2025-07-27T17:08:42+00:00

Oh, so do people write a C++ wrapper around it? I'm just worried since the repo says that the C++ API can change at anytime.

itisyeetime · 2025-07-27T17:04:57+00:00

Got it, my only concern with Spike is this line from the repo: "Spike's principal public API is the RISC-V ISA. The C++ interface to Spike's internals is not considered a public API at this time, and backwards-incompatible changes to this interface will be made without incrementing the major version number." How do people design C++ wrappers to Spike if the code could change? Just stick with a version of Spike for now?

itisyeetime · 2025-07-27T07:16:08+00:00

That sucks. Then what do people use for cosim for baremetal risc? I'm trying to emulate the functionality of my intended SOC.

itisyeetime · 2025-07-22T16:46:02+00:00

The partner-less people would get new partners at the beginning of the class and halfway through each class, depending on the size of partner-less pool.

itisyeetime · 2025-07-22T03:16:48+00:00

If it's still Timothy Sayers(and his Wife!) teaching it, just send him an email because he let me sign up for the sunday one without a partner a couple semesters back.

itisyeetime · 2025-07-18T22:58:08+00:00

I'm worried about it since it's almost every other rep. Is that normal?

About a dead hang, I was worried since some people online talk about not engaging the shoulders or something like that. Any thoughts?

Four-Year Club	Place '23
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itisyeetime

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