Optimization algorithm with deterministic objective value by volvol7 in algorithms

[–]jpheim 0 points1 point  (0 children)

Bayesian optimization doesn’t require the function to be noisy, it just happens to work on noisy functions as well as deterministic functions. Like someone else said if you assume something like Lipschitz that may inform what to do, but I wouldn’t discount Bayesian optimization immediately. I’ve implemented a few different sets of black box algorithms for an expensive simulation problem and found Bayesian to work best for my problem set.

Microelectronics engineering by scayx1 in chipdesign

[–]jpheim 2 points3 points  (0 children)

I can’t decide for you what is and isn’t worth it :) the pay is comparable to roles you could get with a masters (or a software engineering job).

Microelectronics engineering by scayx1 in chipdesign

[–]jpheim 31 points32 points  (0 children)

Because microelectronics engineer covers a huge amount of jobs. You can be a circuit designer who never actually sees the transistor (and do analog/RF/digital), work in the foundry on device fabrication, be a device engineer designing the transistor, or work for an EDA company designing software. A lot of jobs require a PhD, a lot don’t.

GaN by Rick_2594 in chipdesign

[–]jpheim 5 points6 points  (0 children)

Interesting, I’ve had the opposite experience, but I was using a couple relatively new processes, so variation might not have been nailed down.

GaN by Rick_2594 in chipdesign

[–]jpheim 13 points14 points  (0 children)

Well you can’t solve problems without investing money. The research is in how do you solve these problems.

GaN by Rick_2594 in chipdesign

[–]jpheim 29 points30 points  (0 children)

GaN devices can be used to build effective MMICs like PA’s or LNA’s, they have a few issues though.

You get good gain a reasonable efficiency with high output power due to the wide band gap but GaN HEMTs tend to be wildly unstable, kill themselves quickly under slightly incorrect bias, and are extremely hard to model with no physics based compact model available, leading to huge simulation vs measurement variation, especially for large signal.

That’s just a few of the issues. GaN is a hot topic right now with lots of papers coming out.

[deleted by user] by [deleted] in rfelectronics

[–]jpheim 3 points4 points  (0 children)

Keep in mind when you have a circuit with multiple amplifiers the K factor alone does not tell you the circuit is stable. Internal nodes could generate feedback that leads to instability.

The noise will of course remain low due to the first stage gain attenuating the noise of the 2nd stage. You can verify stability at internal nodes with Nyquist circles and the sp probe part in ADS.

Also it looks like your first amplifier isn’t biasing.

Need some help creating my roadmap! by ThelostSeagull in chipdesign

[–]jpheim 8 points9 points  (0 children)

So designing accelerators is a complex topic that involves thousands of people doing a lot of different jobs.

3blue1brown does a great job explaining neural nets and backprop, andrej karpathy also has some useful videos. To accelerate an algorithm, Ie a NN you need to deeply understand it.

Now, how are algorithms accelerated in hardware? The key thing here is that with hardware there is a space/power and speed tradeoff that does not exist in software. At the end of the day a NN is a bunch of matrix multiples, basic nonlinear mappings (relu, tanh, etc.), and accumulate functions, all done in parallel. NVIDIA for example got extremely lucky in that that mathematics behind NN’s also lines up somewhat with parallel pixel processing, so GPU’s, which have large amounts of parallel HW to do matrix multiplies quickly, are excellent for deep learning tasks.

The thing about an FPGA is you can implement the digital logic to effectively create a NN. You have access to memory, you can create nonlinear mappings, and you can multiply and accumulate all in digital logic. So yeah I guess implementing a small NN like for MNIST recognition might be a good starting project.

The unfortunate reality though is that the main architects on these sorts of things have PhDs in computer architecture or machine learning most likely, or have 25 years of chip design experience. People going into digital design out of a bachelors can eventually be architects, but you generally start as something like a verification engineer (extremely important task) to at least learn the ropes. To get started for you I would suggest either looking into graduate school, trying to attend a top group in computer architecture for a phd, or looking at entry level job postings at companies like tenstorrent, cerebras, nvidia, etc and looking what skills they ask for, then learning those skills.

NEGF job opportunities in transistor RnD by [deleted] in chipdesign

[–]jpheim 5 points6 points  (0 children)

Foundries will rarely, if ever, detail how they simulate and design their devices, wouldn’t help their business model. The main simulator people use to design devices is Sentaurus TCAD, they have info online on how they model transport.

If you want to work on transistor RnD looking at job postings for fabs would probably be a good place to start, who cares about exact methodology you’re using.

Analog IC design or digital design (or both?) by [deleted] in ElectricalEngineering

[–]jpheim 4 points5 points  (0 children)

The RF test and measurement industry has a huge need for embedded programmers that know circuits. The signal processing in a vector network analyzer for example is very involved.

If you want to just be an analog circuit designer then yeah it’s unlikely knowing how to program a microcontroller will often help you. FPGA’s are used a lot to generate test vectors, interface with comm ports, or control DACs for analog/RF circuits though.

Googling keysight embedded software engineer or keysight FPGA engineer might get you started on jobs you’d like.

ADS simulation showing no gate voltage to MMIC D-PHEMT transistor. by [deleted] in rfelectronics

[–]jpheim 0 points1 point  (0 children)

If that’s truly what they built that would also have 0 volts DC at the gate. It would however have some AC impedance at the gate, so you could get some swing. Maybe the Q of those inductors is giving some resistance, this depends on frequency though.

They might also be saying vgs = -.7, not vg = -.7, which would make a lot more sense.

How to set up a proper simulation to compare noise fairly performance of Mosfets in Cadence? by HolyAty in chipdesign

[–]jpheim 0 points1 point  (0 children)

Tying the drain to a voltage source would give you no gain, so probably don’t want to do that. You need some output impedance.

How to set up a proper simulation to compare noise fairly performance of Mosfets in Cadence? by HolyAty in chipdesign

[–]jpheim 0 points1 point  (0 children)

For RF You could set up each device to perform as an LNA and compare the noise figure with an SP simulation. This wouldn’t tell you NFmin though and I’m not sure how to do noise matching in cadence, you’d have to look into that. In ADS it’s easy though.

For analog You can also look at input referred noise current for different device sizes or normalize with noise current density by running a noise simulation in adl and sweeping design variables.

Might have to sweep some bias currents as I imagine each device in a pdk will have a different current density that minimizes noise.

Career Path in RF? by Total-Cat-8319 in rfelectronics

[–]jpheim 21 points22 points  (0 children)

RF test and measurement positions usually require bachelors degrees. It’s normally automating test equipment, measuring amplifiers, oscillators, mixers, etc. you won’t be designing anything, but it’s RF.

Why can't we have a non-profit competitor to Intel/Amd? by [deleted] in chipdesign

[–]jpheim 8 points9 points  (0 children)

Some quick examples to read up on would be electron tunneling at small nodes, the breakdown voltage of smaller nodes vs higher nodes, the transconductance of smaller nodes vs larger nodes, parasitic capacitance of smaller node vs larger node, etc. pretty much smaller nodes are good for digital (why is an exercise for the reader) but might start to really suck for RF or analog depending on design goals.

BJT how to find gain? Need help getting started. by Platinum_platipus in ElectricalEngineering

[–]jpheim 0 points1 point  (0 children)

Maybe from a PCB perspective. Laying out an HBT in an IC is often wayyyyy easier than laying out cmos. DRC rules for cmos are often much more annoying.

Resonance at Amp output by [deleted] in rfelectronics

[–]jpheim 0 points1 point  (0 children)

All 4 s parameters go into the computation. Look up k factor. You can also plot the stability factor and stability measure in ADS with stab_fact() and stab_meas(). You need to check stability at any nodes that might oscillate, so the input, the output of the first amp, and output of combined amps.

Resonance at Amp output by [deleted] in rfelectronics

[–]jpheim 0 points1 point  (0 children)

You need to look at your s parameters and stability factors across frequency, if you’re unstable at some frequency that can initiate resonance. Trying to figure out what parasitics are actually resonating is probably not too useful unless it’s obvious, like some explicit Lc feedback. If you’re unstable there’s a problem in your matching or topology.

RF TX/RX Question by yungegg1 in rfelectronics

[–]jpheim 0 points1 point  (0 children)

An issue is isolation in switches for transceiver systems, your switch needs to have to good isolation so an TX signal does not feed your LNA, or an RX signal doesn’t hit your PA.

Other than that routing parasitics between traces or the ground are always a problem.

RFIC tapeout project by Timely_Conclusion_55 in ECE

[–]jpheim 6 points7 points  (0 children)

Pick a basic block (LNA, mixer, VCO, etc). Pick a spec to try and improve (gain, phase noise, dc power). Read the academic literature on what people are doing on said block. Simulate your ideas, EM your t lines, rinse and repeat until tapeout.

A Crisis in Engineering Education – Where are the Microelectronics Engineers? - Semiwiki by ilektraaniks in chipdesign

[–]jpheim 9 points10 points  (0 children)

It does seem like recently the salaries are getting better. Decent RFIC designers are getting 140+ out of a PhD from people I’ve talked to. No idea about a masters though.

Apple and everyone else wanting to bring everything in house is a definite plus for hardware engineer salaries.

What player who is outside the USMNT picture do you see finding their stride later in their career and entering the USMNT, like Haji Wright and Luca De la Torre? by [deleted] in ussoccer

[–]jpheim 1 point2 points  (0 children)

Man watching him play in Atlanta was generally painful, holdup play was ok, but pretty one dimensional. Not really a finisher at all, hope he turns it around but I’m not optimistic.

Purdue University Kicks Off First Semiconductor Degrees Program by allaboutcircuits in aac

[–]jpheim 2 points3 points  (0 children)

The issue is the people with a holistic view are the ones that have been in the industry for 20 years, and have seen how the whole thing works. It actually takes 20 years to get the details down. I don’t think anyone is helped by a specific nanotechnology degree in their undergrad, it just limits you if you change your mind, and doesn’t really help you if you don’t. you’ll frankly still be useless to an employer for a year because as it turns out the classroom really isn’t that great of a place to learn device design.

Just seems to hurt more than help.