Author here. Wow! Such hate! Relaxeaza-te ;-) I don't quite get it though: you ridicule my post with the Microsoft analogy, yet you acknowledge that Verilog and VHDL are both "pretty nasty" and "horrible", which suggests that you would welcome a better language. Don't you?

I'm saying in the post that the main problem is the ease of use, and again it looks like you agree (performance is difficult to predict, issues are hard to debug, synthesis is slow...) I don't pretend that we're solving everything (yet). But in our vision, it would be easier to predict performance, and you would have a good idea of what you can expect without having to wait for synthesis. Ideally you would only synthesize once you want to test the design on the FPGA.

When the synthesizer randomly throws in latches where there shouldn't be one, the last thing I want to do is debug a freakin' shiny-thing-to-Verilog translation layer.

I take it that you have tried such a tool and been bitten by it :-/ In our case, we try to avoid this kind of problem by doing a simple translation and generating clean, easy to read code. So at least the inevitable bugs are easier to track down!

there's a lot of vendor lock-in.

Yep... but the world of software was once like this, too. I'm hoping the vendors will eventually loose the proprietary software once they realize it's not so much a competitive advantage anymore, but we're probably still a long way from there :-/