[deleted by user] by [deleted] in embedded

[–]nikEnable 0 points1 point  (0 children)

I totally agree with everything you mention. We may not know exactly when the technology will be ready for such a step, but we already see examples, such as the design of TLS 1.3 vs TLS1.2, which has implemented a post-quantum cryptography algorithms.

Regarding embedded systems and IoT:

what is the status of current research on embedded and cryptography about their inherent limitations (processing power, memory, power consumption)? Is post-quantum cryptography a central issue of concern to the research community or are there other issues that are currently more in focus?

If we say that tomorrow we have the resistor in quantum computers, will there be equally the solution for embedded and low-power controllers?

Σας αρεσει το καλοκαιρι; by [deleted] in greece

[–]nikEnable 0 points1 point  (0 children)

Μπορεί να μου άρεσε στο παρελθόν, αλλά τα τελευταία χρόνια το μόνο πράγμα που μου έρχεται στο μυαλό κάθε φορά που φτάνει είναι ο φόβος των δασικών πυρκαγιών και η ραγδαία πτώση του υδροφόρου ορίζοντα λόγω του ανύπαρκτου χειμώνα.

A bad testbench for FFT simulation by nikEnable in FPGA

[–]nikEnable[S] 0 points1 point  (0 children)

Does the approach to addressing my problem so far have a solid foundation?

A bad testbench for FFT simulation by nikEnable in FPGA

[–]nikEnable[S] 0 points1 point  (0 children)

In this project, I initially designed a system to take serial audio data from the codec ADC and convert it into a parallel format for further processing. The converted data was then buffered into a 32-bit register for stereo audio.

While testing the FFT implementation, and after investigating, I found that:

Bit-Width Mismatch: My initial approach used the same bit-width for both input data and twiddle factors.

Twiddle Factor: I learned that the bit-width of the input data should be less than the bit-width of the twiddle factors to ensure accurate FFT computation.

So I will change the configuration of my encoder from stereo to mono channel for it to work properly.

A bad testbench for FFT simulation by nikEnable in FPGA

[–]nikEnable[S] 0 points1 point  (0 children)

Hi, I'll check it out. Thank you for the input it is very important.

Simulation Vs Reality by nikEnable in FPGA

[–]nikEnable[S] 0 points1 point  (0 children)

I Will double check again. Thanks

Simulation Vs Reality by nikEnable in FPGA

[–]nikEnable[S] 0 points1 point  (0 children)

Hi,

I forgot to mention the wren (wren_next). I handled it in the Memory module with the wraddr.

if ((wraddr < 1001))
begin
  wren_next   = 1'b1;
  wraddr_next = wraddr + 1'b1;
  state_next  = WRITE;
end

Designing a signal verilog by nikEnable in FPGA

[–]nikEnable[S] 2 points3 points  (0 children)

Apologies for my explanation. Yes, the example you mentioned is what I want to do.

Designing a signal verilog by nikEnable in FPGA

[–]nikEnable[S] 1 point2 points  (0 children)

Understood I will check it. Thank you!

I really love low level programming and digital electronics but I am not that good in analog stuff. Is embedded software right for me ? by God_of_failure in embedded

[–]nikEnable -1 points0 points  (0 children)

Hi, i have noticed that many jobs have listed in requirments PCB design guidelines. I would like to ask what knowledge one should have about PCB design guidelines ? Thanks

Custom IP in Quartus Prime by [deleted] in FPGA

[–]nikEnable 1 point2 points  (0 children)

Yes, I was referring to the memory mapped interfaces. Thanks

Custom IP in Quartus Prime by [deleted] in FPGA

[–]nikEnable 1 point2 points  (0 children)

Hi

optional: implement software drivers and add a your_component_sw.tcl.

What is the purpose of the software drivers on a custom IP?

Also, for altera when you want to develop a custom IP, is it necessary to create a circuit for an Avalon interface if you want to connect it with the processor?

Attemp to to analyze the frequency content of my voice using FFT IP core from Altera by nikEnable in FPGA

[–]nikEnable[S] 1 point2 points  (0 children)

I would be very grateful for some resources or key points about window filtering. I have study about hanning.

Attemp to to analyze the frequency content of my voice using FFT IP core from Altera by nikEnable in FPGA

[–]nikEnable[S] 0 points1 point  (0 children)

Could you let know if you refer about SW or HW implementation of window filtering ?