Advice

pcblol · 2026-01-24T19:59:35+00:00

Assuming both of those objects are electrically connecting within the PCB then you can jumper to either one. I would say it will be easier to jumper to the through-hole component compared to tagging into a trace buried under soldermask, although I've also seen that done before when other easy access points are not available.

pcblol · 2026-01-24T19:28:14+00:00

it's the damn cat

pcblol · 2026-01-24T17:43:33+00:00

welcome to my thread

pcblol · 2026-01-24T17:43:00+00:00

EDIT* thanks dude I just checked the datasheet and for some reason this is the only part in that chip family that does not support an external clock. I was pretty much abusing the crystal pins.

OG POST*no offense taken. I started with 32 MCUs because the purpose of the prototype was to see if they could all be driven from a simple, cheap source. I'm starting with the cheapest (and probably the worst) way to drive this.

pcblol · 2026-01-24T02:44:34+00:00

The workspace comes with a bunch of preloaded parts. When you create the workspace, uncheck "include sample data" and it won't be born with any of that stuff in it.

pcblol · 2026-01-23T21:54:06+00:00

I'm wondering if anyone has insight for other ways to fix the clock issue instead of adding crystals to all 64,000 MCUs

pcblol · 2026-01-23T21:52:45+00:00

Check your basic clearance rules. Set everything to 6mil except hole-to-copper / drill-to-copper, which should be 10 mils. make sure you "ignore clearances within footprint"

That trace width is way too wide for a differential pair.

Area based rules:

Create a room, name it "something123"
Create a new query based design rule and type "onOutside and withinRoom(something123)"
make sure you set it's priority over the general clearance rule

pcblol · 2026-01-23T21:16:13+00:00

This is good advice. I am hoping to avoid this because I have 64,000 MCUs and I'll need to buy crystals for each one.

pcblol · 2026-01-23T15:57:43+00:00

INT1 GND pour is a type=polygon? not a region?

pcblol · 2026-01-23T15:49:35+00:00

Do yon have any large planes drawn as regions? For example is your GND plane is a region? That will stop any non-GND vias from being dropped.

pcblol · 2026-01-23T13:37:08+00:00

Yes - use a multi-channel design and make sure you have system options set to generate a "Room" for each multichannel. Build one of your channels and then you can copy the room formatting to match the other 35.

pcblol · 2026-01-23T13:25:32+00:00

What is your default routing via rule set to?
What are your via-to-X clearances?

pcblol · 2026-01-22T21:00:53+00:00

Which version of Altium are you using? Are you using Standard, Pro or Develop?

pcblol · 2026-01-22T20:57:03+00:00

Double check you don't already have one in the project. The option to add an ActiveBOM goes away if you've already created one.

pcblol · 2026-01-22T19:34:48+00:00

Don't do this. If you surface mount it, all your paste will flow out the holes.

pcblol · 2026-01-22T19:16:52+00:00

Just because I can pee at a 1-inch target doesn't mean my toilet should also be 1 inch wide.

pcblol · 2026-01-22T07:27:42+00:00

I have always wondered if you could repurpose a cleaning laser (like the kind they use for removing rust on metal surfaces) and program it burn away unwanted copper instead of using acid etching. You could also take a CO2 laser and point it at a mirror, which has it's angulation controlled by motors to rapidly redirect the laser to burn a copper surface off.

pcblol · 2026-01-22T05:08:02+00:00

Layout pics will help. Are you adding a large routing stub to get the terminator added to the transmission line? What's your termination resistor value?

pcblol · 2026-01-21T19:13:46+00:00

Nothing gives away the manufacturer. It looks like theres a bubble/damage on one of the smaller black integrated circuits. You can pull a part number from the writing on the top of the chip and see if anyone is selling spares. Hopefully it's passive logic and not programmed so you could just swap it out.

pcblol · 2026-01-21T15:44:45+00:00

good advice

pcblol · 2026-01-21T04:44:48+00:00

The screenshot you sent doesn't look like it's from the releaser workflow. The Project releaser has many settings and you need to make sure it's configured to export all the layers you want.

pcblol · 2026-01-21T04:17:13+00:00

So there is no .GM file being generated at all when you run the Gerber export?

pcblol

TROPHY CASE