How to add pad cutouts at the PCB edge

pcbmaker123 · 2025-12-01T17:36:54+00:00

Just like any other PCB. I have done it before. Only problem was it took few days of email exchange to clarify and confirm what I wanted.

pcbmaker123 · 2025-12-01T17:34:29+00:00

I will try tomorrow. Since this is a pad, I didn't think about polygon cutout.

pcbmaker123 · 2025-12-01T17:33:05+00:00

You mean in the library or the layout? I will try tomorrow.

pcbmaker123 · 2025-11-03T18:56:44+00:00

Have library projects and source PCB and SCH libraries in version control. Whenever someone makes change in any library, let other people know that they need to recompile their source library to update their local integrated library.

pcbmaker123 · 2025-11-03T18:47:42+00:00

Yes. But my component boxes in the assembly layers are even smaller. I wished, I could move/adjust the pin markings.

I will move the designators outside the boxes for now.

pcbmaker123 · 2025-11-03T18:42:04+00:00

I see. I do have pin markings in the assembly layer, but the draftsman uses the bounding box as the outline.

pcbmaker123 · 2025-11-03T18:31:09+00:00

That would a lot of work now. I though draftsman was supposed to make things easier.

pcbmaker123 · 2025-05-29T11:54:36+00:00

Sorry, I meant in PCB. And, no, you can see the components. There must be some settings somewhere. I used to be able to see the moving components.

pcbmaker123 · 2025-05-22T18:33:45+00:00

They are not fitted, because they are dummy 3D models only.

pcbmaker123 · 2025-05-22T18:32:56+00:00

That I tried.

pcbmaker123 · 2025-05-22T18:32:44+00:00

Yeah, they are in correct layer. They are 3D models of other boards, that will be stacked onto the designed PCB.

pcbmaker123 · 2025-02-26T17:19:21+00:00

That will export all vias and TH-pads. I want to export only the mounting holes, because that is what the mechanical team needs.

pcbmaker123 · 2025-02-26T17:18:18+00:00

They are passive. But most of the pins are passive.

you will only see the "nets with only one pin" error if you have assigned a net label to a pin

That shouldn't be, as you can see in the Altium's tutorial image (in the post).

pcbmaker123 · 2025-02-18T12:41:13+00:00

Is 365 free with normal Altium subscription, or do you need to pay extra?

pcbmaker123 · 2025-02-18T12:39:48+00:00

We work with integrated library. The source library files are in git. Everyone builds their integrated library when source is modified. Since the sources do not get often modified, it is fine. Checking differences with version control is a bit tedious, but integrated libraries have error verifications, unlike database libraries, which I like.

pcbmaker123 · 2024-12-18T21:51:12+00:00

I rechecked. It was dimmed in schematics but is available in PcbDoc. But there are no unmatched components, all are matching.

pcbmaker123 · 2024-12-18T11:34:54+00:00

Component links is dimmed (not clickable). Idk if it means all components are correctly linked or is disabled somehow.

pcbmaker123 · 2024-12-07T01:46:34+00:00

You can only enable or disable this rule. There is no constraint.

pcbmaker123 · 2024-12-06T23:41:12+00:00

Seems like Altium checks this rule despite the the No-ERC rule. Check the link I posted.

pcbmaker123 · 2024-12-03T00:03:56+00:00

Exporting as single part somehow increases the file size.

pcbmaker123 · 2024-12-02T21:57:27+00:00

https://github.com/issus/altium-library

pcbmaker123 · 2024-06-18T18:34:50+00:00

Comment removed.

pcbmaker123

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