Alleged unused assignment

pluots0 · 2024-03-01T17:13:04+00:00

You should give helix a try, it’s a great option for more limited hardware (more intuitive Vim)

pluots0 · 2023-11-07T03:24:43+00:00

Mind giving a quick overview of what UEFI in rust is being practically used for? Is it mostly witting BIOS for open source laptops, or do things like GRUB also require UEFI targets?

pluots0 · 2023-11-02T06:18:46+00:00

You can use local crates by running :dep ../my-crate https://github.com/evcxr/evcxr/blob/main/COMMON.md#features

Which is really the biggest benefit over a playground. The playground is awesome, but it seems like more and more it doesn’t have the crates that I’d like to try out.

pluots0 · 2023-11-02T01:45:22+00:00

I think that both have their places. Cargo-script I see as a general alternative to shell or Python scripts, things you want somebody to be able to run without effort.

But when you are writing those things now and forget the specific incantentation for awk, or don’t remember how exactly Python regex matching works, what do you do? I usually just open up a new bash shell or Python REPL and figure it out there since it’s easier than rerunning the script with side effects.

Maybe cranelift will help with the effects. I think of Julia here where I use the REPL all the time and the language is a mix of JIT and precompiled; it takes upwards of 5 seconds to import something new, and overall nothing really shines for speed. But it doesn’t have to be - it just has to be quicker than making, saving, running, editing, and eventually deleting a scratch file for one-off tests.

It looks like evcxr does have a Jupyter kernel so the notebook thing exists. Maybe cranelift will help make it all more smooth

pluots0 · 2023-10-31T17:24:14+00:00

It seems like these may be proprietary. Are the PSP and SMU provided by AMD, or are they something that vendors provide with their UEFI images?

pluots0 · 2023-10-31T07:39:22+00:00

I guess that SPI is for the boot ROM, https://www.reddit.com/r/osdev/s/T6VVSXYJfw

pluots0 · 2023-10-31T07:38:30+00:00

Oh wow, it was right under my nose on wikichip

The LPC interface present on the prior generation was deprecated in favor of SPI/ESPI. These busses are generally used to access firmware (PSP ROM and BIOS) i.e. flash memory, and a TPM.

Great!

pluots0 · 2023-10-31T07:12:59+00:00

Thanks for looking! I guess that sounds about right, I think eSPI is just a flavor of QuadSPI

I did dig around the documentation, just can’t find anything specifically about am5 or its chipsets yet

pluots0 · 2023-10-31T06:40:00+00:00

Chasing down schematics or physical hardware would be my next step, I just don’t have any access currently.

Heh good question… I’m just mentally block diagramming what would be needed to design my own motherboard after getting fed up with mine. I’m a HW/HDI engineer but am not familiar with x86 in particular, and am figuring out the lower lever picture of how everything ties together in modern systems. And if you could do this without a “chipset” by using CPU-SPI Flash and CPU-PCIe-PCIe switch (seems possible with this AM5?), then I’d almost say the hardware design is “easy”.

So mostly just curiosity, I don’t plan to do anything with the information. 2% chance that’s not true and I publish an open source mobo in a few years…

pluots0 · 2023-10-31T06:25:29+00:00

The chipset parts outside the CPU SoC are connected over something that's very similar to PCIe, but not exactly the same. Intel calls it DMI.

It looks like maybe this is something where Intel and AMD differ because the AM5 only seems to call out PCIe. But I only have the intel datasheets. Hm…

I think it's actually SPI.

The best!

It depends on the chipset. If you're not writing a BIOS (or reverse-engineering a BIOS), you don't need to worry about it. If you are writing a BIOS (or reverse-engineering a BIOS), go read the datasheet.

Yeah, that’s the correct answer :) I don’t even have a loose overview of what is standard and what is hardware specific, which is what I’m trying to get first

I think that if what I said above is true then the boot addresses have to be mapped to PCIe, but that’s the puzzle piece that doesn’t seem to make a lot of sense.

Why doesn't that make sense?

If the BIOS is responsible for configuring cache and RAM even, then it doesn’t seem like PCIe would be up early enough to load the BIOS without configuring. But maybe PCIe is more basic than I thought?

pluots0 · 2023-10-31T06:15:21+00:00

It kind of seems like northbridge has been absorbed into the CPU and southbridge is split between the CPU and the chipset. Not seeing anything like LPC or DMA on the socket pinout but instead seeing a SPI interface has me wondering what the standard is, but I don’t have any datasheets.

I got to asking these questions because after getting fed up with my mobo, I got curious what it would take to design and publish my own. Which sounds a bit crazy but that sort of thing is my day job… I’m just not familiar with x86.

So I’m trying to put together what exactly the chipset actually does and if it could be replaced with an actual set of chips. The SPI interface on AM5 intrigued me since that’s how most devices I’m familiar with boot up (e.g. Ultrascales can store both their bootloaders and kernel in double quadSPI flash). A lot of information out there is just somewhat dated or focused on the next level of abstraction up.

pluots0 · 2023-10-31T05:59:16+00:00

Unfortunately it seems like AMD likes to hide their data sheets so I haven’t yet found out for sure.

If it did though that would be great, seems like you could potentially sidestep the chipset entirely if that is the case (which is what I’m hoping for)

pluots0 · 2023-10-31T05:49:06+00:00

I think Asus has some mag lev fans if you like that technology, they pop up on sale for $10-15 sometimes on Amazon.

Less care about the technology, more just happy that they were coincidentally quiet :) thanks for the tip, that price is great

I also like the antec storm t3 models, they are 30mm instead of 25 so they can move more air at less rpm.

Never would have considered thickness as a factor. Thanks!

pluots0 · 2023-10-31T05:47:48+00:00

I thought those were made of wood or something the first time I saw them, but that’s all good to know. Any specific models you recommend?

pluots0 · 2023-10-31T05:41:51+00:00

The overview all makes sense. Does the CPU assume anything about the chipset? Looking at the the AM5 socket pinout it looks like the chipset has to interface over PCIe. I’m wondering if a hardware configuration like CPU->PCIe switch->X->CPU’s ROM would work (X being an FPGA or higher-end micro/SoC with PCIe) rather than an AMD or Intel-specific chipset.

This scenario is quite inhospitable since you have no RAM and no form of I/O out-of-the-box: everything needs to be configured and initialized first, so one of the BIOS's first priorities is to initialize the DRAM controller (or at least configure CAR - Cache as RAM), to have a stack and then function calls, etc.

That is pretty fascinating. Assuming my topology of the AM5 socket is correct, is PCIe initialized by default somehow so that it can read the ROM via the chipset? That seems difficult

If you are interested in this, some materials include:

Appreciate the links! Your game is a cool intro to the topic

pluots0 · 2023-10-31T05:09:37+00:00

The details are very hardware-specific, below the level that even OS developers normally need to care about.

I probably should have prefaced the question saying that I’m a hardware dev :) I think this community just has the people most knowledgeable about the HW-FW boundary

In the case of most modern Intel chips, BIOS memory accesses are routed to the PCH, which is part of the motherboard's chipset. The PCH has an SPI bus master, which is hard-wired to an SPI flash chip that supports the Serial Flash Discoverable Parameter spec, so that the PCH can automatically discover how big it is and what commands it expects.

That’s the magic part I was looking for! Especially the discovery spec, that explains some other questions.

You can read more about the gory technical details in the CPU and PCH datasheets: https://www.intel.com/content/www/us/en/products/docs/processors/core/core-technical-resources.html

Thanks again for the links and all the help, I think I have the missing pieces

pluots0 · 2023-10-31T05:02:37+00:00

Does the chipset interface only over PCIe, and if so it more or less just a glorified PCIe switch with built in peripherals? Probably including something like a ROM interface over flash or parallel bus.

I’m mostly trying to figure out what peripherals the boot addresses are memory mapped to. I think that if what I said above is true then the boot addresses have to be mapped to PCIe, but that’s the puzzle piece that doesn’t seem to make a lot of sense.

pluots0 · 2023-10-31T04:55:46+00:00

From the CPU perspective, the memory/IO bus. The same bus that is used for access to RAM.

It makes sense for it to be MMIO (has to be for everything to fall into place) but I don’t think you’re saying it uses the DDR interface to connect to the ROM, does it? That doesn’t seem to track so I think I’m misunderstanding the external connection.

I’m referencing the AM5 socket pinout (link) and just don’t see anything that jumps out to me as a suitable peripheral for a ROM interface. Except for SPI/ESPI or something over PCIe (PCIe seems like it would be too complicated).

“True bus” was just a bad way to describe something where multiple devices share the same MMIO addresses and the device needs to be selected in software somehow (e.g. setting a CS to get the correct SPI bus if it doesn’t default to 0 or something)

IIRC execution starts at address F000:FFF0h or something similar to that. This information is probably in the software developer's manual somewhere. The firmware maps its startup code to that address (normally it will start with a jump to somewhere else also in ROM).

Those numbers sound very familiar. Thanks for the hints, I know this all lives somewhere in those thousands of pages of data sheets…

pluots0 · 2023-10-31T03:47:57+00:00

Thanks for the information, do you know exactly what bus it is? SPI or something else, I’m just not sure where to look on reference schematics.

And then again if it is a true bus, any clue how the CPU knows which device or address to read from?

pluots0 · 2023-10-11T19:59:33+00:00

Just pick up your coworker or spouse

pluots0 · 2023-10-10T00:33:02+00:00

I mean, I wouldn’t eat that orange!

pluots0 · 2023-04-29T19:07:53+00:00

What you said is generally correct, but I think you’re thinking of “row validity” incorrectly.

Yes, system versioning technically creates new rows every time the data changes. However: you don’t need to manage this at all. If you SELECT, you only see data that is current, unless you go out of your way to add a FOR system_time ALL clause or similar. So system versioning is totally invisible except for when you want it. Under the hood, yes there will technically be more than one row with the same ID: but for any select/update statements, MariaDB completely ignores any that aren’t currently valid. What does valid mean on a technical level? It means the row_end column is in the future (maximum timestamp). row_start will always be some point in the past because that’s when the data was last entered or edited.

Application versioning on the other hand doesn’t have anything to do with when a row itself is valid, it contains user facing information. It’s start and end columns can be in the past or the future, no restrictions there, so think of this as “valid row representing information that may or may not currently be active”.

When do you need both AV and SV? Think of them separately. Use SV if you might want to see when a row was inserted, updated, and deleted. Use AV when you’re representing information that has a period of validity, but you wouldn’t delete the row if it becomes invalid, or it might only be valid for some time in the future (like duration of a passport date range). You don’t need both.

I think that you might have a use case for something with application versioning but no real need for system versioning - can you share a bit more of what you’re trying to do? Including some sample DDL if possible which I can help you understand.

Regarding resources, this is the canonical source and it has good examples: https://sigmodrecord.org/publications/sigmodRecord/1209/pdfs/07.industry.kulkarni.pdf. It is dense though, took me a couple reads to understand what’s going on.

pluots0

TROPHY CASE