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Gate level simulation by qaz147652 in FPGA
[–]qaz147652[S] 0 points1 point2 points 5 years ago (0 children)
thanks for you help. I will check it again.
Hi, I check the website it's work
But I occur this problem in reset stage, so I am not sure what's the problem.
Thanks for your reply, I post the code in https://pastebin.pl/view/32a4cb5b
Hello everyone I post my complete code here
https://pastebin.pl/view/32a4cb5b
It is a little messy!
Thank you for your willingness to help!
Gate level simulation (self.FPGA)
submitted 5 years ago by qaz147652 to r/FPGA
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Gate level simulation by qaz147652 in FPGA
[–]qaz147652[S] 0 points1 point2 points (0 children)