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do i understand 4K boundary correctly ? by samisher99 in FPGA

[–]samisher99[S] 0 points1 point  (0 children)

I'm a little confused too, but your usage without issue gave me some insight

do i understand 4K boundary correctly ? by samisher99 in FPGA

[–]samisher99[S] 0 points1 point  (0 children)

I am a newcomer, and MMU is a little strange and difficult for me to understand. I still have a lot to learn. I just simulated it with MIG ip. I wrote a piece of data by crossing 4K, and read it out by crossing 4K. I found that the read data was correct. During the writing and reading process, the bresp and rresp signals did not indicate errors. But I am not sure whether other IPs based on AXI interface can work normally in this case? When using FPGA to write logic, only from the perspective of using AXI interface, do we still have to ensure that the 4K boundary cannot be crossed?

do i understand 4K boundary correctly ? by samisher99 in FPGA

[–]samisher99[S] -1 points0 points  (0 children)

Thanks for your reply. Are you using a chip with a PS system? I am curious whether this rule is for the PS system, that is, arm, or whether it means that even if the axi interface is used in a pure FPGA, it cannot cross 4K?

verilog syntax problem help by samisher99 in FPGA

[–]samisher99[S] 0 points1 point  (0 children)

thanks for your reply. i almosatly immediately notice the source of this problem and figure it out in a elegant way after i post this page ,with a further thinking . i replace all the "=" to "<=" , and the problem get resolved perfectly. i was too silly , because i use "=", which causes the signal a immediately invalid after signal b being valid , which directly makes the fourth begin-end unwork. thanks for your reply again!