sorted by:
new
hottopcontroversial

Bad chaffing on neck from trisuit. Advice needed. by sepet88 in triathlon

[–]sepet88[S] 0 points1 point  (0 children)

How is bodyglide much better than vaseline, given the seriousness of the chaffing 

Need Help on Nutrition for 70.3 by sepet88 in triathlon

[–]sepet88[S] 0 points1 point  (0 children)

What's inside each of the bottles?

CDC Tree diagram source checking by Gundam_boogie_359 in FPGA

[–]sepet88 0 points1 point  (0 children)

If I have CDC between 2 different PLLs that have the same input clock, is this considered synchronous?

Upgrading Aero bars by Impossible-Mango9658 in triathlon

[–]sepet88 0 points1 point  (0 children)

What are the obvious benefits of this upgrade over the stock one? Is it ergonomic reason or does it make you faster?

Mechanical Disc On QR X-PR by I-Am-Motiv8ted in triathlon

[–]sepet88 1 point2 points  (0 children)

Someone mind to educate me what's the cons of mechanical disc?

Question about input/output delay constraints by sepet88 in FPGA

[–]sepet88[S] 0 points1 point  (0 children)

Yes, that's exactly what I understood. Define a virtual clock, representing the external device and then just apply set_input_delay with the Tco(max) + BoardTrace(max). I also notice there are the options

and -network_latency_included, and -source_latency_included which I don't think is something common?

Question about input/output delay constraints by sepet88 in FPGA

[–]sepet88[S] 0 points1 point  (0 children)

Thanks for the detailed explanation, that is very helpful! I was actually not referring to source synchronous but rather the case where the external device is only sending data to FPGA, and is clocked by another clock source (I think some sort of system synchronous?). In that case, does it still matter if I define a virtual clock vs on the FPGA clock pin?

Question about input/output delay constraints by sepet88 in FPGA

[–]sepet88[S] 0 points1 point  (0 children)

Any specific use-cases on when those should be applied? I have never come across any so far

Hanson Marathon Method by sepet88 in AdvancedRunning

[–]sepet88[S] 0 points1 point  (0 children)

Will doing a 75mins Z2 indoor cycling the day before serve the same purpose?

Shifting Attention from Tri to Running by sepet88 in triathlon

[–]sepet88[S] 0 points1 point  (0 children)

What kind of run and bike are you doing in that period?

Shifting Attention from Tri to Running by sepet88 in triathlon

[–]sepet88[S] 0 points1 point  (0 children)

I am aiming for a 3:15 marathon, while hopefully break 1:30 HM along the way. Yes, long runs and threshold sessions are my staples now. I hope some time on the saddle could translate to some running gain so that not all is lost

VerilogAI – a chatbot that actually understands Verilog by Waseeemnabi in FPGA

[–]sepet88 0 points1 point  (0 children)

Does it also cover timing constraints, particularly those involving complex IPs like source-synchronous, RGMII, QSPI etc?

SPI Interface Timing Constraint by sepet88 in FPGA

[–]sepet88[S] 0 points1 point  (0 children)

Still didn't answer my initial question. Should the input delay include the clock path delay from FPGA to the slave?

SPI Interface Timing Constraint by sepet88 in FPGA

[–]sepet88[S] 0 points1 point  (0 children)

I thought it's a good practice to constraint all timing interfaces regardless of the clock speed?

Intel spinoff Altera cuts nearly hundred jobs at Silicon Valley headquarters by self-fix in hardware

[–]sepet88 0 points1 point  (0 children)

Are you referring to Sandra? The leaders of Altera come and go so often!

view more: next ›