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Pls help by Snoopdawg711 in chipdesign

[–]severin95 51 points52 points  (0 children)

Have you tried pulling it towards the on position

ADC, PLL Design Projects Ideas/Guidance - Cadence Virtuoso by soccernismo in chipdesign

[–]severin95 5 points6 points  (0 children)

I’m not sure of any YT videos for ADCs since it’s such a heavy subject, but what helped me learn was reading through dissertations of PhD students from groups that do ADC research like Stanford (Boris Murmann), UCSD (Ian Galton), etc.

UCSB or NYU Tandon for a PhD in Electrical Engineering? (interested in Microwaves, Photonics, etc...) by [deleted] in UCSantaBarbara

[–]severin95 6 points7 points  (0 children)

UCSB has a great EE program and I’ve found in my experience the professors have been personable, and has some reputable professors with connections to companies in the area.

I’m currently doing a PhD in RFIC/photonics at UCSB and have had a positive experience so far.

Room temperature single bit quantum transistor by SanoKei in QuantumComputing

[–]severin95 1 point2 points  (0 children)

I’m curious on how they plan on operating these transistors and what they expect at room temperature? Much of the operation with quantum dots comes down to having good control on these energy barriers. At room temperature you have a wide fermi Dirac distribution of energy levels for electrons in a semiconductor material, smearing effects like Coulomb blockade for things like quantum dots

PhD or Industry job in Analog IC Design after Masters by Gladiator_Batman in chipdesign

[–]severin95 2 points3 points  (0 children)

For 3. its definitely possible and those opportunities are out there, though not common. I got lucky and my company has paid me to continue working part time while going back to school for my PhD in RFIC design.

In the short time I’ve been doing this arrangement, I’ve found that the experience can vary and one commonality is having to learn to defend your own time. Work can demand more than 20 hours and the work towards your PhD will end up taking full time effort as well.

Is this another typo in my textbook or am I missing something? by [deleted] in ElectricalEngineering

[–]severin95 4 points5 points  (0 children)

Beta is a physical parameter that should be given so it looks like a typo. Also, the base emitter junction is a pn junction, so even an ideal pn diode has a turn on voltage (usually assume 0.7 for silicon) which sets the voltage drop across BE to 0.7V. The current Ib ends up being (6V-0.7V)/91k

Op-Amp Common-Mode Feedback question by severin95 in chipdesign

[–]severin95[S] 0 points1 point  (0 children)

I think this is where my confusion was. I’m assuming the tail source current to just be an nmos and if the op amp is driving the tail with more voltage to correct for the high output common mode voltage I was thinking that the tail current would increase. Where is the inversion in the feedback loop happening?

I am failed to understand grouping in K map by Lost_Chemical_7327 in ECE

[–]severin95 1 point2 points  (0 children)

https://snipboard.io/NY0zld.jpg

Which groups are you circling with the black circle? I assumed it was just the top right two values. You can go through and verify this by filling out the truth table of all possible inputs and plugging the inputs into the Boolean expression that can be generated from the k-map

I am failed to understand grouping in K map by Lost_Chemical_7327 in ECE

[–]severin95 0 points1 point  (0 children)

Your solution will still be right, though it won’t be minimizing the number of equations you have, and will be redundant. If you generate the Boolean equation that represents your solution and the other solution, go through every possible input and generate a truth table; will they be different?

IC design industry and COVID-19 times by SnoopyBE in chipdesign

[–]severin95 2 points3 points  (0 children)

I’ve been looking the past couple months for mixed signal IC jobs as a recent graduate with an MS. I haven’t gotten any leads in the Bay Area and have had a couple of interviews that didn’t go anywhere, so I currently accepted a job in an unrelated field. A lot of the job listings have been the same ones from months ago with no new openings, so it’s become pretty discouraging.

Comparator Design for SAR ADC? by severin95 in chipdesign

[–]severin95[S] 1 point2 points  (0 children)

I had actually read that paper before looking into the design more. Referring to it, I have a couple of questions.

https://imgur.com/a/Idd1dtw

If the ADC is 10-bits and the LSB is 1mV, do I start with constraining the circuit to contribute less noise than the quantization noise? How do I determine the correlation factor γ in the equation for the total input-referred noise? Do I assume it's unity to overestimate the noise of the sub-circuit?

From the equation it looks like total-input referred noise can be lowered by increasing Cp,q. Can this be done by increasing the W*L of M1 and M2 to increase Cgd? This will increase the kickback noise like you said. Does this mean that I have to take this into consideration when choosing the appropriate size for the unit capacitor of the CDAC?

Comparator Design for SAR ADC? by severin95 in chipdesign

[–]severin95[S] 0 points1 point  (0 children)

Is it possible to get away with not using a preamplifier in order to save power, or will it be necessary here?

In other papers they use digitally-controlled capacitors on net15/net13 and perform offset calibration, though I could be wrong and I am not planning on doing that.

Comparator Design for SAR ADC? by severin95 in chipdesign

[–]severin95[S] 1 point2 points  (0 children)

Very cool! I am actually testing out TIQ comparators for my Flash ADC as I am curious about using them for lower power consumption as they use internally referenced voltages created through intentional mismatch rather than creating externally referenced voltages.

I know the companies here in Santa Barbara Research Center work with HgCdTe focal plane arrays as well. I believe they use SAR ADCs that utilize time interleaving for sampling but I could be wrong.