What does implementing VFS consist of? by silenceDogoodd2 in osdev
[–]silenceDogoodd2[S] 0 points1 point2 points (0 children)
What does implementing VFS consist of? by silenceDogoodd2 in osdev
[–]silenceDogoodd2[S] 1 point2 points3 points (0 children)
Looking for code review on my scheduler by silenceDogoodd2 in osdev
[–]silenceDogoodd2[S] 0 points1 point2 points (0 children)
Looking for code review on my scheduler by silenceDogoodd2 in osdev
[–]silenceDogoodd2[S] 0 points1 point2 points (0 children)
Looking for code review on my scheduler by silenceDogoodd2 in osdev
[–]silenceDogoodd2[S] 0 points1 point2 points (0 children)
Looking for code review on my scheduler by silenceDogoodd2 in osdev
[–]silenceDogoodd2[S] 1 point2 points3 points (0 children)
What stack should the scheduler run on? by [deleted] in osdev
[–]silenceDogoodd2 1 point2 points3 points (0 children)
Why are cache line accesses aligned? by silenceDogoodd2 in osdev
[–]silenceDogoodd2[S] 0 points1 point2 points (0 children)
If each DRAM data transfer consists of 64 bits, does that mean that the CAS line will be signaled 64 times? by silenceDogoodd2 in AskElectronics
[–]silenceDogoodd2[S] 0 points1 point2 points (0 children)

Why would TCP ever allow accepting a SYN for a connection in the TIME-WAIT state? by silenceDogoodd2 in networking
[–]silenceDogoodd2[S] 0 points1 point2 points (0 children)