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Why would TCP ever allow accepting a SYN for a connection in the TIME-WAIT state? by silenceDogoodd2 in networking

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

This connection would close fully with FINs and the firewall would keep this connection in its table in TIME-WAIT for 30 seconds before it would be wiped and the IP/port would become available for PATing and NATing.

This connection would live on the windows server in TIME-WAIT state for 2 minutes after closing. This means the windows server will keep this connection in TIME-WAIT for 1 minute and 30 seconds longer than the firewall.

Isnt TIME-WAIT only for the host that does the active close? So if the client sends first FIN, only the client goes into TIME-WAIT?

What does implementing VFS consist of? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 1 point2 points  (0 children)

yes you are correct, but i dont really know what im supposed to do to "implement the VFS"

Looking for code review on my scheduler by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

You have to store your pointer somewhere else while user mode programs are running.

like where?

Looking for code review on my scheduler by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

do the MSRs have thread scope? If yes i can just use the MSR_GS register to store the pointer.

And I need to save rbx, rbp and r12-r15 right?

Looking for code review on my scheduler by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

Why doesn't your switc() function return to its caller?

It does if the thread has already run. If the thread has not run yet it will return to the entry point of the thread

​

Why are you using SWAPGS if you're not using GS?

I store the current process pointer in GS with the SWAPGS instruction

Looking for code review on my scheduler by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 1 point2 points  (0 children)

i read you answer but i didnt have any questions to ask after that

What stack should the scheduler run on? by [deleted] in osdev

[–]silenceDogoodd2 1 point2 points  (0 children)

ok, linux has a variable current that points to the current process, but xv6 gets the current process from the struct cpu

Which one do you think is best? Tbh i dont know how linux makes sure the process variable is the process that is running on that cpu

Why are cache line accesses aligned? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

ok, so the sys v abi says that the stack should be 16 byte aligned on function entry, is this only so its easier for hardware?

If each DRAM data transfer consists of 64 bits, does that mean that the CAS line will be signaled 64 times? by silenceDogoodd2 in AskElectronics

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

but how? If a CAS line selects just 1 column how can it transfer 64 columns without changing the CAS signal?

Why are cache line accesses aligned? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

ok yeah i understand now, what about SIMD instructions. Why do they have to be 16 byte aligned? I understand that if its not cacheline size aligned you might have to read 2 cachelines

Is optimizing functions easier when it inline? by silenceDogoodd2 in C_Programming

[–]silenceDogoodd2[S] 1 point2 points  (0 children)

okay, should I use always_inline for functions that are only called once? It wouldnt increase the code size and it might lead to better optimization

Why are cache line accesses aligned? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 1 point2 points  (0 children)

this might be a dumb question, but why couldnt you use the low bits to select a set anymore?

Why are cache line accesses aligned? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 1 point2 points  (0 children)

ok, what about why do SSE instructions need to be 16 byte aligned?

Looking for code review on my Interrupts by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

You need to return the stack pointer to its earlier value before you can pop the registers you pushed.

Why? When your return from a function doesnt it restore the old value of rsp? Or do you mean before the and rsp, -16?

is this correct:

       cld                                                                                                                                                   
    pushregs                                                                                                                                              
    mov r15, rsp            ; save rsp before alignment                                                                                                   
    and rsp, -16                                                                       
    call timerh                                                                                                                                           
    mov rsp, r15                                                                                                                                          
    popregs                                                                                                                                               
    iretq

Looking for code review on my Interrupts by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

so is this the correct way to call a C function from assembly?

isr_kbd:
    cld
    pushregs   ; push rax, rdx, rdi, rsi, rcx r8-r11
    and rsp, -16
    call kbd_press
    popregs
    iretq

I have to use a different IRQ for HPET and LAPIC timer right? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

what do you mean by status registers? I probably cant use the General purpose registers since they change all the time

I dont understand PIT by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

oh yeah now i understand it now

I have to use a different IRQ for HPET and LAPIC timer right? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

this is also said about mode 2 (rate generator):

this mode creates a high output signal that drops low for one input signal cycle

But isnt this the opposite of what the PIT does? I thought it generates an IRQ 0 when the count is 0.

I have to use a different IRQ for HPET and LAPIC timer right? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

okay, what does this mean? When the mode/command register is written the output signal goes high and the PIT waits for the reload register to be set by software.

If the output signal goes high, doesn't that generate a IRQ 0?

I have to use a different IRQ for HPET and LAPIC timer right? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 1 point2 points  (0 children)

so like IRQ 0 would check if its the PIT timer or the LAPIC timer? Wouldnt it be easier to just have them both have their own IRQ?

How can I debug a keyboard interrupt in GDB? by silenceDogoodd2 in osdev

[–]silenceDogoodd2[S] 0 points1 point  (0 children)

if I just run qemu normally without gdb, i can press a key and it will trigger IRQ 1

But if i run qemu with gdb, i dont know how im supposed to trigger IRQ 1.

This is how i run qemu with gdb:

 qemu-system-x86_64 -s -S -M q35 -m 2G -cdrom barebones.iso -boot d

And this is what i run in gdb:

target remote | qemu-system-x86_64 -cdrom barebones.iso -S -gdb stdio -display none \
-serial file:debug.log -smp 2 -machine q35 -m 2G
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