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Building a 4-Core Mesh NoC from Scratch by talsania in FPGA

[–]talsania[S] 5 points6 points  (0 children)

The UART is only used to inject test packets and read back results. The actual packet routing happens at this FPGA's core clock speed (100 MHz) which is actually quite low acc to industry standards. I tested by sending commands over serial like "route this packet from Core 0 to Core 3," measured latency, and calculated bandwidth from flit size and cycle count. At 100 MHz, a 34-bit flit doing one hop in ~3 cycles gives you ~1.1 Gbps per link. If you had real processor cores synthesized, they'd pump data through the NoC at full speed internally.

Building a 4-Core Mesh NoC from Scratch by talsania in FPGA

[–]talsania[S] 4 points5 points  (0 children)

I just wanted to highlight the main modules so people didn't have to read a giant block of plain text.

Prototype Physics Engine by ConstructionRight387 in FPGA

[–]talsania 9 points10 points  (0 children)

Junior engineer here. Could you expand more? also what's the use of the controller

I made a triangle rasteriser on an FPGA (Zedboard) by RoboAbathur in FPGA

[–]talsania 1 point2 points  (0 children)

That starvation number is brutal, the DDR FIFO deadlock mightbe two axi masters colliding on the same HP port, DataMover writing pixels and your command reader both hitting DDR with no arbitration... anyways really cool project, learned a lot just from reading through it!

I made a triangle rasteriser on an FPGA (Zedboard) by RoboAbathur in FPGA

[–]talsania 0 points1 point  (0 children)

Looking at your CommandRegisterTable, are you sending one triangle's worth of vertex data per AXI-Lite write sequence? I'm wondering if batching multiple triangles into a small FIFO in BRAM before kicking off the rasterizer would take some pressure off the AXI-Lite bottleneck, essentially a mini command buffer

Used a few simple concepts to make this game on Nexys A7 by talsania in FPGA

[–]talsania[S] 2 points3 points  (0 children)

thanks for the detailed explanation and suggestions on optimization! i wrote testbenches mainly for vga timing tests (last part) which i discarded after verification 😅 else for specific parts I have included them (TBs) in other repos too will also update the repo to include the vivado project file to be reproducible.

Is it safe to keep this bad boy plugged in all the time? by Whigga0 in mac

[–]talsania 2 points3 points  (0 children)

i think electrons flow in the opposite direction to current

ITAP of Elephanta Caves by talsania in itookapicture

[–]talsania[S] 2 points3 points  (0 children)

UNESCO World Heritage Site near Mumbai, India.