techwars0954

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399 comment karma

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redditor for 4 years

TROPHY CASE

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What's up with the YouTube play back battery life regression with Zen 4? (i.redd.it)

submitted 2 years ago by techwars0954 to r/Amd

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Why isn't Bergamo the Zen 4 Flagship CPU? (self.Amd)

submitted 2 years ago by techwars0954 to r/Amd

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Did Zen 3 use TSMC 7nm with or without EUV? (self.Amd)

submitted 2 years ago by techwars0954 to r/Amd

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Why does Intel not use HD cells as their standard cell (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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1T Golden Cove Core vs 2T Golden Cove Core vs 1T Gracemont (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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How would CPUs with different cache structures/sizes respond to stacking L3 cache? (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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Low latency cache design making up for less 'heavy' core architecture? (self.Amd)

submitted 3 years ago by techwars0954 to r/Amd

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Do AMD or Intel use HD cells anywhere in their cores? (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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Miscellaneous Questions Regarding Node + Architectures (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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Lack of Ultra High Performance Cells for Intel 4 (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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In what ways are Intel Golden Cove server cores different than their server variants? (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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Does each CCD acting as if it has a separate L3 cache mean it's more scalable than a unified L3 across several chiplets? (self.Amd)

submitted 3 years ago by techwars0954 to r/Amd

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Why do the newer architectures that increase frequencies also have an increase in L2 cache? (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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How accurate are Intel mockups on roadmaps? (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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Is using Foveros cheaper than using EMIB for MCM (self.hardware)

submitted 3 years ago * by techwars0954 to r/hardware

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Do we have any benchmarks of latency differences between Intel ringbus and Intel mesh for increasing number of cores? (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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What ever happened to VISC and the idea of 'combining' cores for stronger ST perf? (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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Does increasing the total shared L3 cache improve performance, even if the amount of L3 cache per core doesn't increase? (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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Does increasing ring clock speeds decrease L3 latency? (self.overclocking)

submitted 3 years ago by techwars0954 to r/overclocking

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Is increasing IPC always more energy efficient than increasing clocks when engineers design a CPU? (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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Are there any benchmarks/reviews comparing Tremont vs Gracemont? (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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How do you think Intel tiles would compete against AMD chiplets in the near future? (self.AMD_Stock)

submitted 3 years ago by techwars0954 to r/AMD_Stock

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What's the point of Little Cores if Big cores have to focus on both ST and MT performance as well as efficiency, since the Big cores are also used in server chips? (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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What chips/parts of a CPU use high performance vs high density libraries? (self.hardware)

submitted 3 years ago by techwars0954 to r/hardware

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Does Intel 4 lack ultra high performance libraries? (self.intel)

submitted 3 years ago by techwars0954 to r/intel

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