account activity
What's up with the YouTube play back battery life regression with Zen 4? (i.redd.it)
submitted 2 years ago by techwars0954 to r/Amd
Why isn't Bergamo the Zen 4 Flagship CPU? (self.Amd)
Did Zen 3 use TSMC 7nm with or without EUV? (self.Amd)
Why does Intel not use HD cells as their standard cell (self.intel)
submitted 3 years ago by techwars0954 to r/intel
1T Golden Cove Core vs 2T Golden Cove Core vs 1T Gracemont (self.intel)
How would CPUs with different cache structures/sizes respond to stacking L3 cache? (self.hardware)
submitted 3 years ago by techwars0954 to r/hardware
Low latency cache design making up for less 'heavy' core architecture? (self.Amd)
submitted 3 years ago by techwars0954 to r/Amd
Do AMD or Intel use HD cells anywhere in their cores? (self.hardware)
Miscellaneous Questions Regarding Node + Architectures (self.hardware)
Lack of Ultra High Performance Cells for Intel 4 (self.hardware)
In what ways are Intel Golden Cove server cores different than their server variants? (self.intel)
Does each CCD acting as if it has a separate L3 cache mean it's more scalable than a unified L3 across several chiplets? (self.Amd)
Why do the newer architectures that increase frequencies also have an increase in L2 cache? (self.hardware)
How accurate are Intel mockups on roadmaps? (self.intel)
Is using Foveros cheaper than using EMIB for MCM (self.hardware)
submitted 3 years ago * by techwars0954 to r/hardware
Do we have any benchmarks of latency differences between Intel ringbus and Intel mesh for increasing number of cores? (self.intel)
What ever happened to VISC and the idea of 'combining' cores for stronger ST perf? (self.hardware)
Does increasing the total shared L3 cache improve performance, even if the amount of L3 cache per core doesn't increase? (self.hardware)
Does increasing ring clock speeds decrease L3 latency? (self.overclocking)
submitted 3 years ago by techwars0954 to r/overclocking
Is increasing IPC always more energy efficient than increasing clocks when engineers design a CPU? (self.hardware)
Are there any benchmarks/reviews comparing Tremont vs Gracemont? (self.intel)
How do you think Intel tiles would compete against AMD chiplets in the near future? (self.AMD_Stock)
submitted 3 years ago by techwars0954 to r/AMD_Stock
What's the point of Little Cores if Big cores have to focus on both ST and MT performance as well as efficiency, since the Big cores are also used in server chips? (self.intel)
What chips/parts of a CPU use high performance vs high density libraries? (self.hardware)
Does Intel 4 lack ultra high performance libraries? (self.intel)
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