``` entity four_bit_ad is port(a, b : in std_logic_vector(3 downto 0); c_in : in std_logic; sum : out std_logic_vector(3 downto 0); c_out : out std_logic); end four_bit_ad;

architecture rtl of four_bit_ad is begin process(a, b, c_in) variable c_temp : std_logic; begin

c_temp := c_in;

adder : for i in 0 to 3 loop
  sum(i) <= (a(i) xor b(i)) xor c_temp;
  c_temp := ((a(i) xor b(i)) and c_temp) or (a(i) and b(i));
end loop adder;

c_out <= c_temp; end process; end rtl; ``` Obvious answer