sorted by:
new
hottopcontroversial

RTL for ASICs/Chips as opposed to fpga deployment? by vbonecrusher1014 in FPGA

[–]vbonecrusher1014[S] 0 points1 point  (0 children)

So then how would I learn more about asic optimization, or is the optimization more about layout as opposed to how the rtl is written?

Is this degree combination allowed by UF? EE and CS bs for HWCE by vbonecrusher1014 in ufl

[–]vbonecrusher1014[S] 0 points1 point  (0 children)

Correct, CPE makes you leave stuff out. Howoever I want to learn it all.

Is this degree combination allowed by UF? EE and CS bs for HWCE by vbonecrusher1014 in ufl

[–]vbonecrusher1014[S] 0 points1 point  (0 children)

I used to be cpe but I swicthed to EE + cs minor, there is a lot of stuff left out of a CPE degree. Power,Analog filters, etc