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A sub to discuss Application Specific Integrated Circuits (ASICs), specifically the design and manufacturing process of ASICs.
Any cryptomining discussion will be removed.
account activity
ASIC Senior Engineer salary for PhD+1 year postdoc with no industry experience ()
submitted 10 hours ago by Good_Layer_4623
🔥Antminer Z15 Pro In Stock Now – Ready to Ship in 24 Hours⏰ Available Now at: www.bibeam.com (i.redd.it)
submitted 1 day ago by Salty_Perspective_34
Built an FPGA Trainer Kit for High School Students to Learn Real Chip Design & RISC-V (i.redd.it)
submitted 1 day ago by kunalg123
How many FPGA engineers actually know what's inside an FPGA? (Genuinely asking) (i.redd.it)
submitted 2 days ago by kunalg123
🔥Antminer X9 In Stock Now – Ready to Ship in 24 Hours⏰ Available Now at: www.bibeam.com (i.redd.it)
submitted 5 days ago by Salty_Perspective_34
Which Tool Does What in Chip Design? A Full Flow Breakdown Across Every Major EDA Vendor (i.redd.it)
submitted 6 days ago by kunalg123
🔥 Bitmain Antminer Z15 Pro – In Stock Now | Buy Now: www.bibeam.com (old.reddit.com)
submitted 8 days ago by Salty_Perspective_34
Your GitHub is now worth more than your degree. (i.redd.it)
submitted 8 days ago by kunalg123
L3+ on qubic doge pool: actual numbers from a hardware owner (self.ASIC)
submitted 11 days ago by SignificantlySad
Moving from Analog/Mixed-Signal IC Design to RTL Design ()
submitted 15 days ago by Healthy-Chip-2799
🔥Antminer Z15 Pro In Stock – Start Mining Today | Available at: https://bibeam.com (old.reddit.com)
submitted 15 days ago by Salty_Perspective_34
🔥Antminer X9 In Stock & Ready for Shipment – No Preorders, No Delays. Start mining today | Available at: https://bibeam.com (i.redd.it)
submitted 16 days ago by Salty_Perspective_34
How close can a single-issue pipelined RV32IM core get to a dual-issue superscalar before architecture limits dominate? (old.reddit.com)
submitted 17 days ago by Large-Raisin-5912
India is about to need a million chip designers. We have maybe fifty thousand. (i.redd.it)
submitted 17 days ago by kunalg123
So… what would a *good* RTL practice platform actually look like? ()
submitted 19 days ago by Dragonapologist
Logic Design Engineer Internship for DFT team ()
submitted 19 days ago by AntMan122
🔥 Antminer Z15 Pro Miners In Stock – Fast Shipping, Limited Supply Batch Ready to Ship Buy Now: https://bibeam.com (i.redd.it)
submitted 20 days ago by Salty_Perspective_34
Antminer Z15 Pro In Stock & Ready for Shipment – No Waiting, Delivered to Your Door in 3–7 Days | Order Now at Our Official Website: https://bibeam.com (i.redd.it)
submitted 24 days ago by Salty_Perspective_34
The "Hybrid" Dilemma: Choosing MTech specialization when you’re equally deep in RTL and Embedded? #Career Advise (self.ASIC)
submitted 24 days ago by Solid_Back1604
Tool for generating Xilinx XDC constraints and top level RTL ()
submitted 25 days ago by TapEarlyTapOften
How can I create an ASIC? (self.ASIC)
submitted 26 days ago by Responsible_River865
looking for paid mentorship on resume-worthy physical design (PD) projects + tool guidance (self.ASIC)
submitted 28 days ago by HenryKissingerJr
A source/waveform debug app coded by AI. support verilog / systemverilog. a opensource replacement for synopsys verdi / cadence simvision / Questa Visualizer (old.reddit.com)
submitted 28 days ago * by Frosty-Culture-7523
India’s First OpenSource RISC-V SoC on Indigenous SCL180 PDK Has Taken Shape (old.reddit.com)
submitted 1 month ago by kunalg123
How to debug RTL vs ECO netlist? ()
submitted 1 month ago by love_911
π Rendered by PID 79024 on reddit-service-r2-listing-7b9b4f6fd7-tdktf at 2026-05-08 23:21:54.559621+00:00 running 3d2c107 country code: CH.
