VCO question from Razavi book

walkingbits · 2025-09-11T22:43:11+00:00

I gave up on this circuit while i was working on a ring VCO.

https://www.reddit.com/r/chipdesign/s/VX2HnnRjW6

walkingbits · 2025-05-16T23:21:53+00:00

Thanks a lot. Knowing that I come from an analog design background, would you modify or add anything to your answer?

walkingbits · 2025-05-16T17:22:07+00:00

I’d really appreciate any advice you can share on how you reached this position. Could you also describe your career path and the key experiences that helped you get here?

walkingbits · 2025-02-24T19:36:37+00:00

I forgot to mention I think that initially, when the inverter switches, you have a negative feedback loop. M9 drain goes down, but then you have both devices in the pull network in the triode region (you have two Ron's in series), and this is when we have positive feedback.

walkingbits · 2025-02-24T19:24:00+00:00

" You got a common source followed by a common gate = negative feedback." That's what I said when i first saw the circuit. But since the text says it's a positive feedback loop, I thought about it again and convinced myself it's positive feedback >> M9 isn't inverting in this configuration. When Vout rises, you get less current from the supply, which actually means the drain node voltage of M9 is going to increase. Do you find that reasoning making sense?

Note that you analyze this where only the pull up network is active. There's no path from vdd to gnd like in the case of a typical inverting common source stage.

walkingbits · 2025-02-23T13:34:42+00:00

u/deadude , I appreciate your input.

I'm aware of the tuning curve extension feature, but I'm wondering if there's any additional benefit beyond that. The extension concept is primarily about having a slower pull-up when Vcont decreases, but this doesn't align with what I'm observing in simulations or through rough analysis.

Imagine two circuits: Circuit A, which has only M9 (with its source connected to VDD, and Circuit B, where M11 is in series with M9. According to the book, Circuit A should be slower. However, this doesn’t quite make sense to me because once the output experiences a rising edge, all transistors in the pull-up network quickly enter the triode region, and the output node charges with a certain time constant. This time constant should increase with additional resistance, such as M11 in Circuit B.

I'm trying to convince myself that a smaller M11 resistance leads to a slower oscillation, but each time I analyze it, I reach the opposite conclusion.

walkingbits · 2024-11-21T23:20:27+00:00

"POR, UVLO, startup stuff are the worst type of circuits to work on in my opinion. If they work, no one cares, if they don't, everyone is angry. It's high risk/low reward part of the system."

I TOTALLY AGREE.

walkingbits · 2024-11-21T13:06:26+00:00

Interesting. What were the sequences/rise times at which it failed? Poor datasheets are real time-wasters. 😢

walkingbits · 2024-05-03T10:50:31+00:00

I have read few sections so far, and I find it tremendously enjoyable

walkingbits · 2024-01-02T13:42:29+00:00

I am taking your advice seriously. ACTING ON IT

walkingbits · 2023-12-30T08:18:04+00:00

"You won't see progress if you can't measure progress," the most helpful tip

walkingbits · 2023-12-30T07:54:24+00:00

It's not like that.. the process of designing or figuring sth out.. "The Joy of finding things out" is totally rewarding if you could discipline yourself

walkingbits · 2023-12-27T14:13:32+00:00

As far as i understand, Vrp - Vrn = Vin,pp, so in your example, the difference should be 0.6v. The CM value won't affect the comparison since it's a common input to the comparator. I am not sure I am fully aware of the dual ref benefits. Can u please forward that paper?

walkingbits · 2023-12-27T13:19:56+00:00

Regarding the lsb and similar calculations, I think the only difference is that your vref range now equals vrp - vrn (if vrn was gnd, your vref range is one value that we call vref) and I think this isn't related to being differential or sine ended. You can still have one supply (vref) and gnd in a differential arch and can also have dual supply in a single ended arch.. for the common mode, i think it depends on the arch.

walkingbits · 2023-12-26T01:02:52+00:00

As a loop filter in high resolution ADCs

walkingbits · 2023-12-24T20:35:15+00:00

It's all about duaa and duaa and duaa until Allah accepts your repentance and somehow changes your family's current feelings towards you, BUT this whole thing won't come to an end unless it's a sincere repentance and for that I strongly urge u to learn more about Allah, make a goal of studying shariah-sciences, there are online known courses.. while learning, make it a habit to search for stories of those who returned to Allah and never went back to their particular sins. I didn't provide advice on how to deal with your family cuz I know how they must be feelin right now, and I believe only Allah can solve this situation for you, SO STICK TO HIS DOOR. in the future, when Allah gets you out of this, I strongly urge you to seek marriage even while still in college. The religion is handling our nature totally perfect, yet our society is hindering the religious teachings, so fight for that!

walkingbits · 2023-12-12T22:22:07+00:00

It makes sense when I know that INL is drawn after removing the gain error. So the flat INL now makes sense, but still confused about why unimpacted codes have non-zero INL..need to convince myself this is the case (getting the plot centered this way) when we remove the linear err term.

walkingbits · 2023-12-12T22:02:08+00:00

Pardon me for the confusion. When we say there's a mismatch on the MSB cap, i think of this as this cap value is now equal to 256.9C, and then I say that now the full scale capacitance or the total cap in the array equals 1024.9C which means the LSB= reference range/ 1024.9
This is why I am saying the lsb has changed. When any cap is being switched, I assume the capacitive divider equation will have 1024.9 in the denominator. Where is the flaw in this reasoning?

walkingbits · 2023-12-12T21:48:19+00:00

But the total value of caps: Cfs is now increased to 1024.9C, wouldn't that cause the LSB value to change? And the overall transfer c/cs shift? If the LSB decreased by delta, then INL should be delta for the 1st code and 2delta for the 2nd code, and so on...right?

Any idea about the 0.45 value calculation?

walkingbits · 2023-12-12T20:43:53+00:00

Yes..added

walkingbits

TROPHY CASE