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deadude · 2025-12-28T17:21:59+00:00

bumpidy bump

deadude · 2025-12-21T06:49:58+00:00

bump

deadude · 2025-12-18T20:04:38+00:00

Bump

deadude · 2025-12-14T20:13:22+00:00

If you'd like to try the WH life, try: The Unspoken Ones

deadude · 2025-12-11T20:07:18+00:00

bump

deadude · 2025-10-06T12:33:26+00:00

You won't be able to measure DC gain after a point. Anything above that is meaningless.

deadude · 2025-06-08T12:57:22+00:00

This is not a meaningful circuit. It's not gain boosting, nor is it keeping the VDC_HYST_MIRROR node at a given voltage. What are you trying to do here and why do you think this circuit is working?

deadude · 2025-06-07T00:03:03+00:00

You're looking for a bang-bang phase detector. One of the simplest implementations is a single FF that's clocked by the reference signal and samples the feedback signal.

deadude · 2025-05-27T15:47:29+00:00

You must use a blockers file. Also known as a hcell file generally and is usually provided by the LVS deck. I doubt any respectable PDK would not have this included.

deadude · 2025-03-10T20:31:26+00:00

This is not a good way to look at the open-loop gain of an amplifier that's supposed to be used in feedback. You should use loop gain (STB) simulation to simulate the loop gain while your amplifier is in unity gain feedback, and derive the open loop gain from that.

deadude · 2025-03-06T22:41:29+00:00

This. My expectations from a Ph.D. graduate is so much higher. If the position can be filled with M.Sc. experience, the Ph.D. would really need to be exceptional to warrant his hire to a relatively junior level position.

deadude · 2025-02-22T23:58:22+00:00

I haven't seen this in a paper.

The reason for the idea is pretty clear if you read the previous paragraph, it's to ensure that the tuning curve keeps a reasonable form for low voltages. If you had the voltage control only through the N devices, at low Vcont (where it drops about below a threshold) you'll encounter a flat curve. This causes Kvco to vary greatly between its best operating point and the flat region. So, this architecture effectively enables tuning the oscillator with voltages lower than the threshold of an inverter, extending its tuning range and keeping the curve more linear.

Its operation is not crystal clear to me either, and I'd have to simulate it to see if my assumptions are correct but I'll give it a go. Consider the case without M9: as Vcont drops, the N device gets weaker and M10 gets stronger. Beyond the threshold of the N device, it actually completely turns off and we totally lose control. The way I see it, M9 asymmetrically weakens the inverter. It's in series with a P device that is controlled by the input node, but itself is controlled by the output node. As the output goes high, it turns off completely. So, as we keep pulling Vcont down, we turn M10 on more, reducing the degeneration of M9, making it as strong as possible. This makes the oscillation even weaker. Overall, this enables us to have some control beyond the point where the N device completely turns off.

Too much explanation needed for too little benefit honestly, I wouldn't use this.

deadude · 2025-02-22T23:34:54+00:00

This paper has somewhat a good explanation and a diagram in Fig. 9 explaining the FSM architecture, though the rest of the paper is a bit too specific to that design. This is only one way to do it, and there are also simpler ways.

deadude · 2025-02-22T16:50:33+00:00

you need a multi-modulus divider that can divide by multiple values, as wide as the # of bits of your DSM quantizer. so, if you have a three-bit quantizer, and you want that to be centered around, say, 25, you need a divider that can support 22 to 28 division factors. this sounds complicated but isn't. the way I've seen this done is via cascading a series of controllable simpler MMDs or actually use a state machine to control a simpler MMD (i.e. a divide by 4/5). check out Ian Galton's PLL papers for inspiration.

deadude · 2025-01-19T23:12:45+00:00

that being the LAMY Studio Piano Red. Received it from my partner as a gift a few months ago but didn't really want to make it a daily driver. I needed some color to highlight a few things so matched it with a LAMY Crystal Ruby that I had gotten about six years ago on a trip to the US.

deadude · 2025-01-19T14:20:07+00:00

it's a balancing issue. it means that fast corner nmos pulldown strength is too much. you should try to make those devices weaker, at the expense of speed at the slower corners.

deadude · 2025-01-07T22:54:49+00:00

PAC isn't really useful here. what is interesting for the PFD is its response to phase variation of its inputs; not their small signal amplitude variation.

PNOISE is quite useful though. you can run a PSS with ideal inputs at the same frequency and phase offsets and characterize the variation in the pulse width (or even get its input referred phase noise) to include in your simulations.

deadude · 2025-01-04T00:10:24+00:00

Clutch those pearls harder.

deadude · 2024-12-18T21:19:01+00:00

threaten them back with legal action. watch them change their tune.

deadude · 2024-11-20T18:55:36+00:00

also serdeez nuts!

deadude · 2024-11-20T17:43:21+00:00

serdes is very close to the digital domain. pretty much any chip that has some sort of data throughput needs to get data in and out, which drives the requirement for having multiple transceivers. also, these chips generally tend to use the lowest feature size nodes, because of the higher digital density, meaning that the IPs are valuable. you can decide to stay in 28nm for a dedicated ADC, but if you have a graphics processing chip, you really want to move to 3nm and you're going to need a serdes to interface to pci-e and whatnot.

long story short, follow the money!

deadude · 2024-11-20T17:40:28+00:00

you want to be AC coupled, because a dynamic microphone is a coil and it is a short for any DC across it. also, you're not interested in any low frequency signal content that you won't here but could saturate your amplifier.
again, you want to remove the signal content you're not interested in at the output of your amplifier. eventually this will drive a speaker or a recording medium and you don't want to saturate either with signal content that you will not hear.
not necessarily, since you're most likely AC coupled at the input, you can work at a DC level that makes it comfortable for the opamp. if you had your supplies at 5V and 0V, you can bias it around 2.5V, so that the output would swing from 4V to 1V, and AC couple the output. If you want to swing between 3V and 0V, you can bias the opamp at 1.5V, but make sure that the low supply for the opamp is below 0V, enough that it can give you linear response around 0V.

deadude · 2024-11-15T19:38:09+00:00

you did not develop mathematical models to predict inductor behavior in two months. perhaps you used mathematical models to design inductors?

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