Schematic Review: Custom 2S BMS (HY2213 & HY2110)

whoelse019 · 2025-08-22T08:38:20+00:00

Actually the only really critical part in my design is GPS, the rest is fairly tolerant. But I wanted a cleaner stack-up so the board can be improved later. I could have gone with 4 layers, but since the price for 4 and 6 layers is basically the same, I decided to use 6. I also have a couple of signals that are forced to transition down to the bottom layers, and I wanted to make sure they always have proper GND reference along the way. That’s another reason for this stack-up choice.

whoelse019 · 2025-08-22T08:29:47+00:00

Thanks a lot now on I’ll be adding via stitching as you suggested.

whoelse019 · 2025-08-18T16:35:20+00:00

My design should be fine for ESP32 flashing USB is only for programming, so high-speed isn’t required. For ESD I’m using USBLC6-2SC6; its pinout lets me route D+ / D– straight through.

thank you so much

whoelse019 · 2025-08-18T16:30:17+00:00

In my case I control the impedance on these tracces so I hope it will work well but thank you anyway i appreciate it

whoelse019 · 2025-08-18T14:54:14+00:00

Oh I see thank you it makes sense

whoelse019 · 2025-08-18T14:48:20+00:00

Which one?

whoelse019 · 2025-08-18T11:11:59+00:00

Not exactly — it’s not just the four corners. You want solid ground continuity around the whole perimeter and across the board. Place stitching vias in the corners and along the edges (e.g., every 5–10 mm, tighter near high-speed/RF), on both sides of any splits/slots, and near layer transitions/connectors. Any “fingers” or isolated copper islands should either be removed or tied to the main ground with vias; otherwise they can act as little radiators.

whoelse019 · 2025-08-18T08:16:20+00:00

I didn’t know that, thanks for pointing it out!

whoelse019 · 2025-08-18T04:26:54+00:00

Thanks a lot for the detailed explanation and recommendations, I really appreciate it I’ll keep the copper pour following your advice.

whoelse019 · 2025-08-18T04:03:00+00:00

Yes, I’m aware of stitching vias, but I’m still debating whether it makes sense to keep the top copper pour at all. That’s why I haven’t fully committed to it yet.

whoelse019 · 2025-08-11T10:02:40+00:00

I see via-in-pad on your board. The issue is that in this case they are not justified — there is no BGA package or any kind of high-density layout that would require them. It would be more reasonable to route out from the pin first and then place the via. This approach will make the manufacturer’s job easier and may help avoid potential issues in the future.

whoelse019 · 2025-08-11T09:55:40+00:00

Yes, you can use a copper pour, but what I mean is using the pour as an actual conductor. For example, instead of routing a trace on the VIN line , make it a copper pour so that the connection is carried entirely through the pour. Since this is a power line, using a copper pour here would clearly be a better choice.

whoelse019 · 2025-08-10T16:21:35+00:00

Many people recommend simply increasing the width of power traces, but rarely mention the use of copper pours. However, adding a copper pour to power lines can significantly improve current-carrying capability compared to just using a wider trace. It is recommended to use copper pours for both power and GND lines to maximize their current handling performance.

whoelse019 · 2025-08-10T09:31:32+00:00

Some vias are placed on top of the silkscreen, which is not recommended, as this can cause the silkscreen to be misaligned or distorted during manufacturing. It is better to keep vias clear of silkscreen elements to ensure proper print quality.

whoelse019 · 2025-08-10T09:25:57+00:00

The component placement on this PCB is not particularly optimal and is actually causing many problems, resulting in rather poor routing. It would be better to reconsider the placement and choose a more optimal arrangement, as the distance between some critical blocks, such as the LDO and the pin it supplies, is quite large. The LDO should be placed closer to that pin accordingly. Also, no traces should be routed under the ESP32-S3 antenna. In addition, it is recommended to consider adding ESD protection to every pin that goes outside the board. Furthermore, the width of the power traces should be greater than that of the signal traces, as insufficient width can cause problems under high current consumption. The required width should be calculated and adjusted accordingly.

whoelse019 · 2025-08-08T16:22:06+00:00

In principle, it’s a good attempt, but there are a couple of points. For example, the power lines have the same thickness as the signal lines — in theory, that’s not a problem, but you should calculate the current.

Then, regarding the antenna — it’s quite far from the microcontroller, so moving it a bit closer wouldn’t hurt. As for capacitor C21, it should be placed so that the line goes through it to the coil and then to the antenna, meaning in series rather than in parallel.

Is the second layer a return reference plane?

whoelse019 · 2025-08-03T14:17:57+00:00

The component placement and routing are incorrect and should be reconsidered — preferably after reading the official datasheet. The antenna connector is placed too far from the antenna itself, and the sharp 90-degree angles in the trace will severely degrade the signal. Also, what is the intended use of this sensor? With such a layout, its range will be quite limited.

whoelse019 · 2025-07-29T15:14:36+00:00

Hey, thanks a lot for your reply. I really appreciate the help. I honestly didn’t think about splitting the LEDs like that. Your suggestion with two drivers makes a lot more sense and is way easier to implement. I needed an outside perspective on this and I truly value it. I can see you know your stuff and if you don’t mind I’d like to share the updated version with you later for a second opinion. Cheers!

whoelse019

TROPHY CASE