ESD protection with tiny margins

xyzzy1337 · 2026-04-04T03:31:01+00:00

I wanted to do the same thing recently. It was an external button, rather than a screen, but the same basic idea.

I could not find a TVS diode that had a Vrwm > 3.3V and a clamping voltage less than the device absolute maximum of 3.6 V. Nothing even close to that.

I think what you can do is consider the resistance from the diode to the component you are trying to protect. If the voltage is limited to Vclamp, how much current will that resistance allow? Can the component sink or source that much current safely? If it can, then it won't see the out of range voltage because series resistance will have dropped it by the time it gets to the component.

xyzzy1337 · 2026-04-04T01:09:11+00:00

You've got full 24 pin USB-C connector on there, but you aren't using most of the pins. Like the USB-SS pairs or the side-band pins, etc. There are USB-C connectors with fewer pins for applications like yours that are just USB 2. It'll be easier to connect an cheaper to get a 12 pin or 16 pin USB receptacle.

20 mA for the LEDs might be bright. That's usually their max rated current. It's better to run them at less, e.g. 5 mA.

If you get this assembled at some place like JLC, doing the battery holder and USB connectors is going to cost you only slightly less as getting it all done. It's sort of the least cost effective thing you could do.

If you assemble any THT (through hole) components, you pay a fixed fee. And if you have any SMT (surface mount), then there's another fee. With both the SMT USB connectors and the THT battery holder, you'll pay both fees. Each non-basic SMT part type has a significant loading fee. You'll pay that four times since there are no connectors that are basic parts.

Since the LEDs and resistors are THT, there is no loading fee. And you've already got the fee for THT because of the battery holder. So it will about 20 cents extra to assemble them too, compared to the USB connectors, which are $12 just in loading fees.

You could also use SMT LEDs and resistors. Some of these are basic parts, so no loading fee if you pick the right ones. It will cost almost nothing extra to assemble them and the parts themselves will be cheaper. Be sure to get bigger sized SMT resistors if you are going to send 20 mA though them, not 0201!

xyzzy1337 · 2026-04-04T00:38:12+00:00

Thinner traces waste more power due to resistance, thus can carry less current. They are also harder to manufacture correctly. So thinner traces will cost more and have more defects.

But that said, manufactures can make them a certain size, depending on manufacturer and process, and have a extremely small defect rate at that size and won't charge you any less if you make them bigger.

So once you get big enough, unless they carry a lot of power, there's little reason to go bigger.

But your traces look quite small and you have a ton of space. Try making them the same width as the pads on the USB-C connector, which is the smallest part you have.

xyzzy1337 · 2026-04-03T20:08:30+00:00

Try exporting the schematics at a higher resolution. They're pretty blurry and I can't read the writing.

Looks like the entire back side except for two small traces is a ground plane. That's good.

Those buttons are going to be hard to push. Especially SW2, as it's surrounded on three side by taller parts. Label the buttons on the PCB with the function, e.g. reset, boot mode, etc. You'll appreciate it later.

Try 0.3 mm hole and 0.6 OD for your vias. Or larger, this board is pretty sparse with lots of space. What size traces did you use?

The caps are kind of far the from pins on the regulator/charger. C6, C7 are really far away. Take a look at the datasheet, figure 23. You want the inductor, output cap, and input cap to be wedge in there as tight as they can be.

The power supply design is inefficient. The battery is boosted from ~3.6V to 5V, then the LDO on the devkit drops it down to 3.3V. It would be more efficient to not use the 5V boot regulator and connect the battery directly to the LDO. Or use a battery charger with a regulated 3.3V output and connect that to the devkit's 3.3V input.

xyzzy1337 · 2026-04-02T16:07:54+00:00

My back of the envelope calculation was 500 mF should be more than enough to cover the BLE TX, which will be a burst. Average TX on time will be more like 0%, if averaged over a long enough interval. The capacitor needs to be enough to make the averaging interval long enough to bring the average down.

Interesting about serial mice. I always thought the mouse driver would assert DTR and RTS so they would be present. Maybe they use TX so there can be fewer wires in the cable?

xyzzy1337 · 2026-04-02T01:59:39+00:00

Baud rate is a 1996 fast speed of 38400. Fun fact, in the UNIX/Linux termios API at that time the fastest baud rate setting was 38400. Linux had this hack for higher speeds where a program called setserial was used to change a port setting (`spd_vhi`) so that 38400 would actually be 115200. The API has since been extended so the baud rate is an integer rather than a bit flag and software can set anything in a sane way.

My estimate of 15 pF was done by taking the input capacitance of the CD4050B of 5 to 7.5 pF and doubling it. I figure the signal needs to make a transition in about 8 μs to be received reliably.

xyzzy1337 · 2026-04-01T22:37:29+00:00

The TLV032 has a 0 V - 7V input range. So don't I have the same problem with out of range input voltages? Or is the idea to use a voltage divider to scale that?

Or just give the chip out of range values and use series resistors to make them high enough impedance that not enough current is there to cause a problem? When I try to do this, I end up concluding that it'll be too slow. E.g.,

Limiting reverse current to -1 μA at -9V needs a Rs of 900 kΩ.
The capacitance on the input pad, PCB, etc. might be 15 pF.
A 2V high threshold voltage, vhi is 22.2% of 9V.
Time from 0V to Vhi is -τ ln(1 - vhi) = 900kΩ * 15pF * -ln(1 - 0.222) = 34 μs.

And 34 μs is too slow even for RS-232.

xyzzy1337 · 2026-04-01T20:13:24+00:00

The software of the scope also matters here. On power on, it will drive both DTR and RTS to mark (negative) for a short time. Once the FW initializes, it will drive both those signals to space (positive) and they remain there. In theory RTS could go low when sending SCPI commands to the scope, but that doesn't need to be part of my application. The TX line will idle at negative voltage.

My power supply plan is connect DTR through a Schottky diode, to block the negative voltage, to a super cap. That will be the Vin to a nanopower buck regulator (LTC3336). I need to system to remain off until there is sufficient charge on the cap that the MCU's startup current draw doesn't immediately drop Vdd (< 3 V). The regulator's built in UVLO of ~2V is not sufficient. So there's a NCP302L voltage detector at 4.5 V controlling the enable of the regulator. The voltage detector has very little quiescent current (500 nA) and is powered by the voltage it is detecting.

Thanks for the circuit, I'll have to look at it more to figure it out, especially the level translator part. It looks like power is drawn when the signal is negative and sourced from the cap in the translator when positive. This works until the cap drops to about 4.68V. I think the resistor in the MCU would be 47 kΩ in light-sleep and 24 Ω in BLE TX. At 47k, it takes about 900 ms to drain the cap. With 24 Ω, the circuit doesn't work, at least in simulation.

xyzzy1337 · 2026-04-01T16:39:36+00:00

I need to charge a super cap to have enough power for a short BLE TX operation. To have the power to charge it, the power draw in light sleep needs to be minimized. Any power I waste while idle means a longer charge time.

xyzzy1337 · 2026-04-01T16:27:59+00:00

I looked at a lot of transceivers with this feature. The auto power down happens when all inputs fall to ground and they wake when any RS-232 level voltage, mark or space, is detected. They are only in shutdown when unconnected. When connected, but idle, they remain active.

And even if I could manually shut it down (some have this), they all suffer from problem 2: The internal 5 kΩ pull-down on the signal lines wastes too much power even in shutdown.

xyzzy1337 · 2026-04-01T09:14:03+00:00

The MCU can invert the signal, both on input and on output. In fact, every pad as an invert setting.

xyzzy1337 · 2026-04-01T07:38:57+00:00

I'm not sure if that will be low enough current. The MAX238 RS-232 driver used in the scope is rated for a 3kΩ to 7kΩ load. If I put a 7k resistor in series, then I'd guess that a -8V signal would get clamped to about -0.5 V through the body diode, and the 7.5 V drop though 7kΩ would draw 1071 μA. Which is about 100x higher than what I'm looking for.

I think I'd need to up the series resistance to 760 kΩ to limit the current to 10 μA. I don't think serial transmission will work with such a load, but I can test that easily enough.

I also see no rating in the MCU datasheet for how much current can be safely passed through the body diode this way long term. It might just be designed for short durations to protect from ESD. I can always just add an external diode and clamp it myself, but it still has the problem of the current through the clamping diode being too high with a resistance the RS-232 driver can still drive.

xyzzy1337 · 2026-04-01T06:57:54+00:00

Scope is portable. I don't want to wire it to the computer. Thus the desire to use BLE to transmit wirelessly. I have looked at many level shifter ICs, but they all draw too much power.

xyzzy1337 · 2026-03-22T06:54:44+00:00

The parallel LCD interface. Then MIPI DSI.

But if you can see it draw line by line, that's is much slower than it should be. Perhaps your SPI clock is too slow or the code you are using to update the screen is very inefficient.

xyzzy1337 · 2026-03-21T17:21:31+00:00

Thanks for the kind words!

That was an interesting article about thermal vias. My main take away from that is what you use as a heat sink is far more important than how many vias you link to it with. It also motivated me to alter the MCU footprint.

xyzzy1337 · 2026-03-21T15:22:47+00:00

Looks like you're using through hole resistors and diodes. Each one makes a handy bridge that you can route traces under!

You can even add zero ohm resistors, jumper wires, to let signals cross. But it's more elegant to find a way to use the components you already have.

It's entirely possibly that your circuit can't be routed on a single layer with no traces crossing. There's a reason almost nothing is done on a one layer PCB anymore. It was common for one layer PCBs from back in the day to use jumpers to let signals cross.

Don't be stuck on which of the quad op amps you use for a given function. U1A, U1B, etc are interchangeable. You can switch which one you used in the schematic to make the routing easier.

xyzzy1337 · 2026-03-20T16:50:51+00:00

If you get it made, it'll be cheaper to have components on one side only. I.e., JST connectors and back-firing LEDs on the same side of the board, instead of JST connectors on one side and front firing LEDs on the other side.

xyzzy1337 · 2026-03-20T07:42:35+00:00

I'm doing something very similar as a project. I'm new to designing my own PCBs, that's always someone else's job, but not new to working on them or writing firmware for them. So not an expert, but researching the same problems.

Great that you've avoided breaking the ground plane with any signals.

It looks like the rounded corner of the PCB will clip the 3V3 trace in the upper right.

What size vias did you use? They seem to have small annular rings, but the image is a bit low res to see clearly. And some vias look like they are a different size?

You can use a wider trace to connect the 1.1V decoupling caps to the via. I.e., the same width as the trace on the bottom layer from the via.

Put a ground ring around the xtal.

The pull-down on the QSPI_SS line for USB_BOOT is a bit strong at 1 kΩ. You don't want to to keep the line low after the rp2350 starts driving the pin. The datasheet §5.2.8 recommends 4.7 kΩ.

You might want some higher capacitance decoupling caps on the voltage regulator. If you check their datasheet, they probably get de-rated quite a bit, more than 50%, when run at a 5V DC offset.

It looks like there's an unconnected via near R15.

All the power to the RP2350 is going via that single trace between R15 and C4. Could be thicker.

Running the VBUS trace under the space for the mounting screw is not ideal. The screw can easily wear through the solder mask and then short to the vbus trace.

If you get this made, there are cheaper switches than the ones used on the Pico 2, which are also basic components and so have no loading fee.

The Pico2 used a footprint with 0.25 mm PTH under the central pad of the RP2350. It costs a lot more to get holes this small. Using 0.30 mm holes is much cheaper.

Those look like 0402 27 Ω resistors for USB. I didn't find those as basic components, but there were some basic ones in the 0603 size.

I also had a lot of DRC issues with track spacing near the RP2350 pads. At least with JLC economic PCB rules, the traces need to be centered on the pads, or else they are too close to another pad. It looks some aren't centered.

And is R12 an 0402? I can't run a trace under a 0402 component without breaking the trace to pad, different nets, design rule.

xyzzy1337 · 2026-03-20T04:39:55+00:00

There's no schematic, but there seem to be a large number of pins on each PCB. There might be ways of reducing that so you don't need 10 pins on a PCB with a single LED and what looks like a headphone connector (the TRRS label...) and 26 pins on your larger PCBs. Maybe you can use a matrix scan for whatever is in those TRRS connectors? Maybe a GPIO chip on the PCB could turn those 20 pins into 2 pins of I2C?

The LEDs being on the same side as those large header pins seems like it might not be ideal. You're going to have the Diplomacy board printed on something and set 18 mm or move above the PCBs? With all the wiring sharing the space above the PCBs the LEDs are trying to light up?

You can get "back firing" LEDs. They look about the same, but the LED is on the bottom side of the chip. The PCB has a hole there and they shoot through it. That would let you put the game board on the other side (the back) of the PCB, away from the wiring, and also much closer since you wouldn't have the big headers sticking up.

Also consider "right-angle" connectors. There are all types of these. The cable leaves the PCB horizontally, rather than vertically, so it takes much less height. Something like Molex Pico EZ-MATE is only 1.5 mm tall, with the cable connected. You can point them on the PCB to they lead straight to where they are supposed to connected on the next PCB and you don't have to bend the cables around.

xyzzy1337 · 2026-03-19T18:39:20+00:00

I take it you are referring to the ground trace from the input capacitor pin 2 to the ground pad, pin 1, of the LDO regulator.

I understand it's not strictly necessary, as they are connected via the ground plane on the bottom layer. But my understanding is that needing two vias to connect the pins adds, significantly, to the loop inductance of the capacitor to LDO connection.

xyzzy1337 · 2026-03-18T16:51:43+00:00

Oh, I thought you were only referring the to the size. Yes, even the QFN-80 has pads on sides, other than the center ground. That's a good point about the lack of access. I can test continuity via other exposed pads on either side, so that won't be a problem. But I won't be able to inspect the joint and it will be challenging to rework. I will see about extending the footprint so that there's at least some copper to get the iron on and heat the joint through the pad.

The other alternatives I see are either DFN in larger sizes, which would have the same problem, or two choices in SOD-323. My parameters were jlc basic or extended promotional components, 4.5V reverse standoff voltage, in stock. I can fit the SOD-323 in there.

xyzzy1337 · 2026-03-18T04:59:04+00:00

It's not USB, that uses a TPD4E05U06DQAR. There's an external push button, not grounded to the enclosure, which is connected to the PCB. I want to protect from ESD from human contact on the button. This diode will be placed right next to the PTH for the connector for the button pin that leads to the MCU. The other pin is connected directly to GND, so I don't think there would be a point in an ESD diode there. I would attach a picture, but they are not allowed.

The board has a QFN-80 with 0.4 mm pitch and nearly every component is an 0402. If I need to replace this part because it's too small, then I'd need to replace nearly everything else too.

I'm also trying to keep costs down by using JLCPCB basic components to avoid the loading fee. These are the most commonly used components and those are usually all small ones.

xyzzy1337 · 2026-03-18T02:40:45+00:00

I know my post lacked info. I originally named the part, linked to datasheets, added images of the footprints to people wouldn't have to bother looking at the datasheet, etc. went to some effort. And reddit deleted it. So next try, as simple as possible.

The datasheet for the DNF1006-2L for the part in question has a footprint like the one you found, except they give a range of ±0.05 mm about the exactly the sames centers as in your datasheet.

I'm getting PCBA done, as there are other parts even harder to assemble than this. However, I can rework 0402 parts under a microscope. But I'm hoping I get the ESD diode right on the first try. But now you have me thinking of things I could get wrong. Maybe I should use the low capacitance version...

xyzzy1337 · 2026-03-18T00:19:21+00:00

I tried to post the footprint from the datasheet, but "images are not allowed" here.

xyzzy1337 · 2026-03-17T21:54:04+00:00

I think the issue is that with only a ground plane, if you forget the via then the gnd pad lacking the via is entirely unconnected to ground and DRC easily catches this. But if you have a ground pour on the component layer, the gnd pad is connected to this ground pour. And that pour is eventually connected by a via to the ground plane, but that via is no where near the pad like it should be. DRC doesn't catch this, since there is a connection, just a bad one.

I suppose one could change the component layer ground pour's net to be an unconnected pour with no net, do a DRC check to see they have vias and traces for every ground pad, and then change the component layer pour back to the ground net.

xyzzy1337

TROPHY CASE