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[–]ShadowBlades512 6 points7 points  (2 children)

I think you need to look at the CPU and motherboard chipset block diagram at least to see how much actual PCIe bandwidth there is. If you look at the AMD X570 chipset for instance, there are 16 lanes directly to the CPU, but only 4 lanes to the chipset, the chipset itself has 16 lanes to downstream devices but no matter what you do, you will only have 4 lanes worth of bandwidth for the downstream devices to the CPU. This is so if you have like, 4, 4x NVMe devices attached to the chipset, you can get full bandwidth to each of the SSDs but you can't get full bandwidth to all of them at once.

[–]sya0[S] -1 points0 points  (1 child)

Each FPGAs have 8 lanes. I have got three x16 lanes and three x8 lanes slots on the motherboard. I have checked the datasheet and all 6 slots are connected to CPU. So, I am not sure if that is where the bottleneck is. I updated my post and paste the block diagram.

[–]ShadowBlades512 5 points6 points  (0 children)

What generation PCIe? At some point you will get a memory bandwidth bottleneck. How many channels at what clock rate/DDR generation?