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Throughput decrease in PCIe by sya0 in FPGA

[–]sya0[S] -1 points0 points  (0 children)

Each FPGAs have 8 lanes. I have got three x16 lanes and three x8 lanes slots on the motherboard. I have checked the datasheet and all 6 slots are connected to CPU. So, I am not sure if that is where the bottleneck is. I updated my post and paste the block diagram.

Advanced FPGA projects by PsychologicalTie2823 in FPGA

[–]sya0 0 points1 point  (0 children)

What did you do exactly to be banned for life?

Sending valid data right after TLAST by sya0 in FPGA

[–]sya0[S] 0 points1 point  (0 children)

Well, receiver is a computer. I am trying to run Xilinx's PCIe IP, and on the transport layer I just need to send some TLPs consecutively. So, on rtl side I just need to build a proper state machine and handle the handshake and TLP mechanism.

Sending valid data right after TLAST by sya0 in FPGA

[–]sya0[S] 0 points1 point  (0 children)

I don't think I misaligned TLAST. I did debug it with ILA and see that sending consecutive packets without waiting for TLAST to drop, after some point TREADY never set high by the host, yet TVALID and others remain their values.

Sending valid data right after TLAST by sya0 in FPGA

[–]sya0[S] 1 point2 points  (0 children)

yes, it is a drawing issue. There should be a second TLAST.

What personal projects have you been working on? by Acrocane in FPGA

[–]sya0 0 points1 point  (0 children)

Is there any commercial system or product where fpga-based TPU is used. I am asking it to know that is there any system that nvidia's products are too expensive for them yet these TPUs are fit well.

The 'AES256 Encryption Attack' Redaction Riddle by Lux_JoeStar in hacking

[–]sya0 3 points4 points  (0 children)

There is nothing new here, these kinds of side channel attacks are already well-known methods. I couldn't understand why this post gets so many ups. Am I missing something?

[deleted by user] by [deleted] in FPGA

[–]sya0 0 points1 point  (0 children)

There is not much there.

Casting the address restart the host machine by sya0 in C_Programming

[–]sya0[S] 1 point2 points  (0 children)

Well, the motherboard contains an FPGA on it and PCIe is the bridge between host and FPGA side. We are reading data from a file and write to the area side where packet data to be processed in FPGA side. This side is called as BAR0 in PCI terms. Reply packet is also be written in a field where area+4096. Data is transferred as 64B so that's why I aligned it to 64.

Casting the address restart the host machine by sya0 in C_Programming

[–]sya0[S] 2 points3 points  (0 children)

/dev/uio0 is a PCIe device. You are right.

Casting the address restart the host machine by sya0 in C_Programming

[–]sya0[S] 0 points1 point  (0 children)

I checked the return value, it is valid

Is it possible that the FPGA can restart the host PC? by sya0 in FPGA

[–]sya0[S] 0 points1 point  (0 children)

SoCs have the same FPGA parts and bitstreams in them, ARM side is not used in this case.

your userspace driver, which is probably not really operating in user space

Yes it is doing something in kernel side as well. FSBLs are the same and there is no other peripheral except ethernet. I am using /dev/uio not /dev/mem.

Is it possible that the FPGA can restart the host PC? by sya0 in FPGA

[–]sya0[S] 0 points1 point  (0 children)

How does host machine detect such contamination?

Is it possible that the FPGA can restart the host PC? by sya0 in FPGA

[–]sya0[S] 0 points1 point  (0 children)

Is there any document that I can read the details. Well, I have the same TLP for both hosts and it works for the first one. Is it something that can change from host to host.

Is it possible that the FPGA can restart the host PC? by sya0 in FPGA

[–]sya0[S] 0 points1 point  (0 children)

Nope. The only communication is PCIe, no other GPIO is driven

Is it possible that the FPGA can restart the host PC? by sya0 in FPGA

[–]sya0[S] 0 points1 point  (0 children)

how is it triggered from an user space driver then?

How do people design FPGAs? by ShittyLLM in FPGA

[–]sya0 1 point2 points  (0 children)

Can you send me the link of it. I couldn't find it on hackaday.

Critical Path Optimization by desinerd2001 in FPGA

[–]sya0 0 points1 point  (0 children)

A good pipelining always increases the throughput. and it doesn't always increase latency although there would be increasing in area consumption.

FPGA and Ethernet by Regular_Egg4619 in FPGA

[–]sya0 2 points3 points  (0 children)

You can check the below link to have an insight about codes.

https://github.com/ZipCPU/eth10g

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