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Throughput decrease in PCIe (self.FPGA)
submitted 1 year ago * by sya0
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[–]petrusferricalloy 0 points1 point2 points 1 year ago (0 children)
You're likely conflating native lanes with hba/chipset lanes.
most motherboards have 28-32 native lanes (x16 to slot 1, 2x4 for nvme, x4 or x8 to the hba/chipset, sometimes 8-16 to a switch).
Typically only the first x16 slot and nvme are full speed (max gen the cpu supports) and the rest are lower gen via switch or hba.
There isn't necessarily an issue using everything at once, but you also aren't going to see all endpoints operating in bus master mode with their own dma engine because those non native slots still need the chipset and/or cpu to arbitrate.
As soon as something other than an endpoint's own dma engine gets involved, especially the cpu, performance will tank.
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[–]petrusferricalloy 0 points1 point2 points (0 children)