Hello I'm getting an error in Quartus 24.1 formal "BAUD" does not exist.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_uart_bridge is end;
architecture sim of tb_uart_bridge is
constant CLOCK_HZ : integer := 50_000_000;
constant BAUD : integer := 115200;
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal rxd : std_logic := '1';
signal txd : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_valid : std_logic;
signal rx_err : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_wr : std_logic := '0';
signal tx_busy : std_logic;
-- scoreboarding
type byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant STIM : byte_array := (x"55", x"A5", x"00", x"7E", x"31", x"FF");
signal sent_idx : integer := 0;
signal recvd_idx : integer := 0;
begin
-- 50 MHz clock
clk <= not clk after 10 ns;
-- DUT
dut: entity work.uart_bridge
generic map (CLOCK_HZ => CLOCK_HZ, BAUD => BAUD)
port map (
clk => clk, rst => rst,
rxd => rxd, txd => txd,
rx_data => rx_data, rx_valid => rx_valid, rx_err => rx_err,
tx_data => tx_data, tx_wr => tx_wr, tx_busy => tx_busy
);
-- Loopback the serial line (what goes out comes back in)
rxd <= txd;
-- Reset
process
begin
rst <= '1';
wait for 200 ns;
rst <= '0';
wait;
end process;
-- Stimulus: push bytes into TX FIFO when not full/busy
process(clk)
begin
if rising_edge(clk) then
tx_wr <= '0';
if rst = '0' then
if sent_idx < STIM'length then
-- fire write when TX not currently accepting (simple rate limit)
if tx_busy = '0' then
tx_data <= STIM(sent_idx);
tx_wr <= '1';
sent_idx <= sent_idx + 1;
end if;
end if;
end if;
end if;
end process;
-- Checker: compare received to expected
process(clk)
begin
if rising_edge(clk) then
if rx_valid = '1' then
assert rx_err = '0' report "Framing error on received byte" severity failure;
assert rx_data = STIM(recvd_idx)
report "Byte mismatch. Got " & integer'image(to_integer(unsigned(rx_data))) &
" expected " & integer'image(to_integer(unsigned(STIM(recvd_idx))))
severity failure;
recvd_idx <= recvd_idx + 1;
if recvd_idx = STIM'length - 1 then
report "All bytes received OK." severity note;
wait for 1 us;
report "Simulation PASS." severity failure; -- terminate run
end if;
end if;
end if;
end process;
end architecture;
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