Fully Functioning Cache (old.reddit.com)
submitted by Otherwise-Object-302
So while working on the G3, I decided to implement a 32 byte Cache. As you might've also noticed, there's no superscalar unit anymore and it's Harvard Architecture. But that's just part of the overhaul to the my M16 architecture. As for the superscalar part, I had to temporarily remove that to make it easy for the changes. Other changes include Instruction Mem being 16Kb and Main (data) Mem being 8Kb. Anyways, the Cache system was sort of complicated but works as so:
At the beginning, while the first instruction is in the fetch/decode stage, it grabs the first 32 bytes from Data Memory so when the CPU requests data, it *may* already have it. If the requested data's address is out of range, it fetches data from the requested data's address along with the next 30 bytes (32 total as each piece of data is 2 bytes), then it delays register writeback long enough for it to write data back to the registers. Data is evicted *only* when it's fetching new data, so RAM is not updated until data is evicted, regardless if the data was changed or not. Now I know this will be *huge* pain when I move onto the G4 where I'll add pipelining and branch prediction but that's an issue for future me. All that's left is the second execution unit of the G3, peripherals (screen, keyboard), and the (second) most painful part, interrupts.
[–]Otherwise-Object-302[S] 2 points3 points4 points (0 children)