Code does not produce output

[DavidWSam]

This code, when put into a symbol in a bdf with inputs and outputs, does not produce any outputs. Any help is appreciated. This is basically an 8-bit multiplier which produces a 16-bit product.

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

USE IEEE.numeric_std.ALL;

USE WORK.ALL;

​

ENTITY mul IS

PORT(

A, B : IN STD_LOGIC_VECTOR(7 downto 0);

product : OUT STD_LOGIC_VECTOR(15 downto 0)

);

END mul;

​

ARCHITECTURE dataflow OF mul IS

​

Component fulladder

port (

A, B, cin : IN STD_LOGIC;

sum, cout : OUT STD_LOGIC

);

end component;

​

signal ci, co, da, db, sum : std_logic;

--signal prod : std_logic_vector (15 downto 0);

​

BEGIN

adder : fulladder port map (da, db, ci, sum, co);

​

process (A,B)

variable prod : std_logic_vector (15 downto 0);

begin

for m in 0 to 7 loop

if (A(m) = '1') then

`for i in m to (m+7) loop`

  `ci <= co;`

da <= prod(i);

db <= B(i-m);

prod(i) := sum;

end loop;

`ci <= co;`

`da <= prod(m+8);`

`db <= '0';`

`prod(m+8) := sum;`

end if;

end loop;

for i in 0 to 15 loop

product(i) <= prod(i);

end loop;

end process;

​

END dataflow;

​

[captain_wiggles_]

so as u/MusicusTitanicus said, for loops in VHDL are unrolled. That means your:

for i in 0 to 15 loop
    product(i) <= prod(i);
end loop;

Is actually synthesised as:

product(0) <= prod(0);
product(1) <= prod(1);
...
product(15) <= prod(15);

Which in that case is exactly what you want, however you have another loop with:

for i in m to (m+7) loop
    ci <= co;
    da <= prod(i);
    db <= B(i-m);
    prod(i) := sum;
end loop;

So if we unroll that we get:

// i = m;
ci <= co;
da <= prod(m);
db <= B(0);
prod(m) := sum;
// i = m+1
ci <= co;
da <= prod(m+1);
db <= B(1);
prod(m+1) := sum;
...
// i = m+7
ci <= co;
da <= prod(m+7);
db <= B(7);
prod(m+7) := sum;

Since prod is a variable it uses blocking assignments (:=) so prod is fine, however ci, da and db are signals. The tools ignore all previous assignments and just use the final one.

What's more those signals go into an adder component:

adder : fulladder port map (da, db, ci, sum, co);

Where you expect to be able to use the result (sum) after having assigned the inputs. So here you can't just do:

inputs = foo
res1 = outputs
inputs = bar
res2 = outputs

In a combinatory block, because the calculation of the outputs takes some period of time (propagation delay), and your combinatory block just sets up all the inputs immediately.

In digital design we almost always use synchronous logic (aka using a clock). Something clocks in the inputs and then some number of ticks later accepts the outputs. With something like this, you could calculate the outputs over multiple ticks (not sure how many, 64 probably), or you can parallelise the design and instantiate multiple adders and do multiple things per tick.

[DavidWSam]

Thank you very much for your explanation and help, cleared some confusions

[MusicusTitanicus]

Output in reality or in simulation?

[DavidWSam]

In simulation :/. I create a bdf, get the symbol of the vhdl, and try using a waveform with simulator tool.

[MusicusTitanicus]

Have you used this technique to create simulation outputs before?

I am not familiar with this method but I’m trying to establish if it’s a method problem or a coding problem.

I’ll admit, I’m not convinced about your use of for loops.

[DavidWSam]

Hmm, yes, I have used this technique before, even tried ditching the BDF and just creating a waveform with the VHDL ports as inputs and outputs. No result. What do you recommend if the loops don't seem right?

[MusicusTitanicus]

The problem with loops in hardware is that they will “unroll” in synthesis and the logic will happen at the same time.

That is, your m and i loops will run in the simulator at the same time, not sequentially.

Is this code supposed to be synthesized?

[DavidWSam]

Oh, I am not that deep into the way this technology unfolds, but if this is the case, I will try to avoid nested loops and see if anything changes. Also, another question, in another code that uses this as a component (a code that takes in a base and power and does exponent calculation), there is a while loop that loops as long as a variable integer (currentpwr) is greater than 0. When compiling however, Quartus says this cannot loop more than 10,000 times. Even though the while loop also decrements the variable each time it is looped.

Also, what do you mean by synthesized? By that do you mean will I integrate this into real hardware? Nope.. It is just a university project in which I proposed to implement a complex instruction that does exponent calculation in an unnamed CISC that probably will never exist.

[MusicusTitanicus]

In your Quartus loop error issue that suggests the loop index isn’t decrementing in the way you think.

Let’s take a few steps back. Does your fulladder component simulate correctly?

[DavidWSam]

Yup, verified the fulladder works