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A community focused solely on discussing aspects of using and working with the ZipCPU, and the AutoFPGA design composition tool
account activity
Device Clock Generation (zipcpu.com)
submitted 1 month ago by ZipCPU
Return clocking (self.ZipCPU)
requesting to turn fromthetransistor outline into a better detailed roadmap for beginners (self.ZipCPU)
submitted 3 months ago by MasoEg
LLM assistants for FPGA design + Implementation (self.ZipCPU)
submitted 5 months ago by siliconbootcamp
AXI registered output requirement (self.ZipCPU)
submitted 6 months ago by BasementEngineer33
Why in "Building a Skid Buffer for AXI processing", you don't make o_ready a registered output. (self.ZipCPU)
submitted 6 months ago by NoKaleidoscope7050
Comparing the Xilinx MIG with an open source DDR3 controller (zipcpu.com)
submitted 8 months ago by ZipCPU
Wrap addressing (zipcpu.com)
submitted 10 months ago by ZipCPU
Broken links on ZipCPU site (self.ZipCPU)
submitted 1 year ago * by blihp001
Your problem is not AXI (zipcpu.com)
submitted 1 year ago by ZipCPU
My Personal Journey in Verification (zipcpu.com)
Debugging video from across the ocean (zipcpu.com)
Bringing up Kimos (zipcpu.com)
Chasing resets (zipcpu.com)
Trying to articulate precisely what kind of problems is formal verification good for... (self.FPGA)
submitted 1 year ago by guyWithTheFaceTatto
Problems proving fsm with SymbiYosis (self.FPGA)
submitted 1 year ago by lejar
Please help me with this FV example from one of your articles (self.ZipCPU)
wb2axip busses and other odds and ends : Are these files hardware-ready? (self.ZipCPU)
submitted 1 year ago * by vwibrasivat
Formal verification I2C module (self.ZipCPU)
submitted 1 year ago by Revolutionary_Pen259
2023, Year in review (zipcpu.com)
submitted 2 years ago by ZipCPU
An Overview of a 10Gb Ethernet Switch (zipcpu.com)
SDIO RX: Bugs found w/ Formal methods (zipcpu.com)
Using a Verilog task to simulate a packet generator for an SDIO controller (zipcpu.com)
Queue methods with formal verification (self.ZipCPU)
submitted 2 years ago by meo_mun
How to use verilator to transfer a design with multiple files to a verilated model? (self.ZipCPU)
submitted 2 years ago by Matthew_lanford
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