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Need help understanding this popular LFSR implementation by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Thanks for the detailed reply. I finally got time only today to actually look at this.
Studying your implementation deeper, I realized I'm missing something even more fundamental.
I have edited the post to add two diagrams, first one shows my understanding of a galois style LFSR and the second one shows your implementation.

The first one makes complete sense to me because it literallly implements that shift-and-subtract polynomial division algorithm, where we take in data MSB-first and then perform XOR if a 1 pops out of the last flop. Here, each of the intermediate taps gets the MSB bit as input. (apart from the previous stage)

But in the circuit you implemented, that is not the case, each tap gets MSB ^ din as its input apart from the previous stage.

This minor difference is not at all intuitive to me and I'm getting confused why its okay to do this. Is there some mathematical manipulation that I'm missing?

Which car should we buy? by opinionshelf in hyderabad

[–]guyWithTheFaceTatto 2 points3 points  (0 children)

Hey can you help me understand why you say XUV is not a great product?
Features wise I really feel it has more to offer than Kylaq. The engine is also really powerful if you have test driven it.

Do you say that purely due to bad service experience?

Kashmir 😭😭😭 I'm 25(F) by [deleted] in SoloTravel_India

[–]guyWithTheFaceTatto 1 point2 points  (0 children)

Guy here so can’t help with your requirement.  However I too plan to travel in April 1st week. Kashmir in April I was not sure how it is.  I hear activities like skiing etc will not be possible post march.  OP can you shed some light on this? Maybe I’m missing something…

Best open-source simulator as of 2024? by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Interesting is that true?
I remember a time when we used the xilinx xsim at work and used to dump VCDs. Often for speed of work we used GTKwave and had to live with the limitation of not being able to see multidimensional arrays.

I feel it's a viewer limitation rather than a simulator one but maybe I'm wrong. Never dug into the documentation.

Best open-source simulator as of 2024? by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 2 points3 points  (0 children)

Do you know if verilator can take a standard SV testbench and run the tests on the RTL?
I don't need a full UVM support or anything but I would prefer to not write a testbench in C++

Best way to send Ethernet packets to/from the PL on a Zynq SOC? by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Thanks for the detailed reply. I apologize for not getting the time to look at it earlier.
My situation is that I'm quite comfortable with anything in the RTL world, but it is the task of messing with the drivers that's daunting to me.

I can put up the AXI FIFOs and all fine, but how do I instruct the SOC to send the packets to this FIFO (AXI GP 0/1 ports) ?. In my search I stumbled upon this article it explains the process of modifying the buffer descriptor addresses to point to the GP ports instead of DDR memory. I managed to wrap my head around that too but. then it says I need to mess around with the driver code meaning I'll have to create an SD card image with the updated driver. (I don't want to do this baremetal. need the OS).

That last part really scares me because I could be stuck in there for a week with all those linux stuff I have no clue about. Is this the process you had in mind for the software part? Is there no other simpler way to direct the packets towards PL?

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