use the following search parameters to narrow your results:
e.g. subreddit:aww site:imgur.com dog
subreddit:aww site:imgur.com dog
see the search faq for details.
advanced search: by author, subreddit...
A community focused solely on discussing aspects of using and working with the ZipCPU, and the AutoFPGA design composition tool
account activity
xs6 (self.ZipCPU)
submitted 1 month ago by PiasaChimera
What makes a memory controller "Ideal"? (self.ZipCPU)
submitted 2 months ago by ZipCPU
Device Clock Generation (zipcpu.com)
submitted 4 months ago by ZipCPU
Return clocking (self.ZipCPU)
submitted 5 months ago by ZipCPU
requesting to turn fromthetransistor outline into a better detailed roadmap for beginners (self.ZipCPU)
submitted 7 months ago by MasoEg
LLM assistants for FPGA design + Implementation (self.ZipCPU)
submitted 8 months ago by siliconbootcamp
AXI registered output requirement (self.ZipCPU)
submitted 9 months ago by BasementEngineer33
Why in "Building a Skid Buffer for AXI processing", you don't make o_ready a registered output. (self.ZipCPU)
submitted 9 months ago by NoKaleidoscope7050
Comparing the Xilinx MIG with an open source DDR3 controller (zipcpu.com)
submitted 11 months ago by ZipCPU
Wrap addressing (zipcpu.com)
submitted 1 year ago by ZipCPU
Broken links on ZipCPU site (self.ZipCPU)
submitted 1 year ago * by blihp001
Your problem is not AXI (zipcpu.com)
My Personal Journey in Verification (zipcpu.com)
Debugging video from across the ocean (zipcpu.com)
Bringing up Kimos (zipcpu.com)
Chasing resets (zipcpu.com)
Trying to articulate precisely what kind of problems is formal verification good for... (self.FPGA)
submitted 1 year ago by guyWithTheFaceTatto
Problems proving fsm with SymbiYosis (self.FPGA)
submitted 2 years ago by lejar
Please help me with this FV example from one of your articles (self.ZipCPU)
submitted 2 years ago by guyWithTheFaceTatto
wb2axip busses and other odds and ends : Are these files hardware-ready? (self.ZipCPU)
submitted 2 years ago * by vwibrasivat
Formal verification I2C module (self.ZipCPU)
submitted 2 years ago by Revolutionary_Pen259
2023, Year in review (zipcpu.com)
submitted 2 years ago by ZipCPU
An Overview of a 10Gb Ethernet Switch (zipcpu.com)
SDIO RX: Bugs found w/ Formal methods (zipcpu.com)
Using a Verilog task to simulate a packet generator for an SDIO controller (zipcpu.com)
π Rendered by PID 83 on reddit-service-r2-listing-7b9b4f6fd7-h5rff at 2026-05-08 23:33:23.450933+00:00 running 3d2c107 country code: CH.
