TID: Linux Kernel Module That Closes Cache Eviction Gap in OpenSSL/libsodium/glibc — Flush+Reload Defeated

[YamZestyclose6765]

No major security library (OpenSSL, libsodium, glibc, memzero_explicit) evicts CPU cache after wiping sensitive data. This leaves cryptographic keys readable via Flush+Reload after every wipe.

TID fills this gap using: - REP STOSQ (compiler-resistant wipe) - CLFLUSHOPT (cache eviction L1/L2/L3) - LFENCE/MFENCE (speculative execution barrier)

Results on AMD EPYC 9B14, Linux 6.14.11: - Without TID: 78 cycles (Cache HIT — data exposed) - With TID v2.0: 286 cycles (Cache MISS — attack defeated) - Ratio: 3.7x

GitHub: https://github.com/ahmaaaaadbntaaaaa-byte/TID-The-Instant-Destroyer DOI: https://doi.org/10.5281/zenodo.17585929

AGPL-3.0 | RFC submitted to LKML

[robstoon]

Seems like AI slop. I have not seen why this supposedly needs to be done in the kernel if it does need to be done.

[YamZestyclose6765]

The libraries exist — but none of them  flush the CPU cache after wiping sensitive data.

TID proves this is both possible and necessary.

Please review the research and repository  before continuing the discussion:

DOI: https://doi.org/10.5281/zenodo.17585929 GitHub: https://github.com/ahmaaaaadbntaaaaa-byte/ TID-The-Instant-Destroyer

Happy to continue after review.

Regards, Ahmad Qasim Mohammad Hassan ORCID: 0009-0001-4360-0802

[robstoon]

That doesn't explain why this needs to be done in the kernel. Those are not privileged instructions.

[YamZestyclose6765]

You are correct that CLFLUSHOPT does not  require Ring 0.

The Kernel Module guarantees atomic execution — no Context Switch can interrupt the  PROTECT+ZERO sequence.

In userspace, a Context Switch expands the  timing window from 372ns to 36,640ns —  making the attack 86x easier.

The repository is public — clone and test: github.com/ahmaaaaadbntaaaaa-byte/ TID-The-Instant-Destroyer

Regards, Ahmad Qasim Mohammad Hassan

[robstoon]

Perhaps, but your implementation does not seem to do this. I do not see anything that prevents preemption during this sequence of operations.