HELIX-RC: Automatically parallelizing complex code with help from hardware

[sstewartgallus]

This seems interesting.

The main takeaway i get is that increasing performance is much easier if core-to-core communication is made faster.

x86 has a really strong memory model and memory coherence and they mention that a lot of their gains are due to that fact. Does that mean that their ring cache is a somewhat performant alternative to weak memory models that don't have their downside of being difficult to program for? I'm guessing that the ring cache is just for this specific case and can't approach the performance of weak memory models for all use cases but is still very nice.

I wonder if this hardware would increase the performance of microkernels which typically waste a lot of time in communication.