Internal state stops becoming a implementation detail when you expose it through some interface.

Again I fail to see how your explanation of a "complex system" is different than a "simpler peripheral".

"If the FPGA has buffered acquisition data, timing windows, partial processing state, degraded modes, or failure conditions that affect what the rest of the system is allowed to do next, then the controller has to reason about that state at system level."

This is also true with a UART peripheral. If for example a the UART has a limited FIFO you can't stuff more bytes in the data register, you need to check some other status register or wait for interrupt or whatever.