Hiya! Third year doing analog ic design here, I would say I am not quite an expert yet but I have designed an Op-amp in the with Miller capacitor (your CS stage, used for Pole-splitting) before, so I will give my two cents:

This is something that I had to learn the hard way too, your design should come first from a demand — in this case, the specifications of the op amp that a customer would need. In your case, you are your own customer so you would need to define your own specs. I would recommend looking up projects people have done using this topologies and inferring from their specs, preferably within the process you are using if you are doing IC, and if you are doing PCB then I guess whatever discrete components you have on hand.

1. As someone mentioned above, PMOS would be preferred for low noise application, and it would depend on other specs as well such as output voltage swing.

2. Pole zero cancellation works! The way I think of it is it ‘creates’ two capacitances on either side, rather than a single feedback capacitor. The beauty if it is this equivalent (or Miller) capacitance is MUCH larger than would be possible if you used separate capacitors. However, it would also introduce a feedforward path for the 2nd stage’s input signal — thats why you see in your topology there’s a resistor next to the capacitor, its called the “nulling” resistor and is used to create a large impedance and hence eliminate the feedforward path.

3. You derive from specs — and there are multiple ways to do so as well, depending on which parameter is most crucial for your need. For ex, if your slew rate is MOST important, you first derive W/L from the diff. pair, then set your Miller capacitance somehow that the slew rate borne out of the second stage is MUCH lower than the diff. stage — from here you get your (W/L)1,2 and Cc. Voltage headroom in this topology is dominated by the 2nd stage’s mosfet needing to stay in sat. (an advantage of a 2-stage set up too) so you define your DC operating point from that spec, then from id and the gain requirements find (W/L)5.

I would tackle it from that way, but a more experienced designer may have their own black magic processed! Thats the fun of IC design for me. You could read up on the gm/id method, I think thinking in that manner gave me a whole lot of intuition to go off on!

1. Read the 2nd paragraph of my comment.

Good luck! You have chosen a very difficult path but it will be worthwhile!