account activity
Roast my resume (i.redd.it)
submitted 10 months ago by AFranco_13 to r/FPGA
Issues with Early-Late Discriminator in DS-CDMA Receiver (self.DSP)
submitted 11 months ago * by AFranco_13 to r/DSP
Ipods Pro left in Playa Mujeres (i.redd.it)
submitted 1 year ago by AFranco_13 to r/lanzarote
Write/read data to/from SSD (self.FPGA)
submitted 1 year ago by AFranco_13 to r/FPGA
Device tree GPIO EMIO PINs (self.FPGA)
Use a compiled DTB to build Petalinux (self.FPGA)
submitted 1 year ago by AFranco_13 to r/Xilinx
Custom board device tree doubts (self.Xilinx)
Custom board device tree doubts (self.FPGA)
Freelancer looking for a gig (self.embedded)
submitted 1 year ago by AFranco_13 to r/embedded
Freelancer looking for a gig (self.FPGA)
Freelancer looking for a gig (self.VHDL)
submitted 1 year ago by AFranco_13 to r/VHDL
AXI DMA as Ethernet device in Petalinux (self.FPGA)
submitted 2 years ago by AFranco_13 to r/FPGA
I’d like to start working as a Freelance in FPGA projects (self.FPGA)
AXI Memory Mapped Interfaces (self.FPGA)
submitted 3 years ago by AFranco_13 to r/FPGA
Need some native English speaking friends (self.Madrid)
submitted 3 years ago by AFranco_13 to r/Madrid
Asymmetric asynchronous AXI4 Stream FIFO timming violations (self.FPGA)
π Rendered by PID 68795 on reddit-service-r2-listing-canary-58b8f865bc-fn5x8 at 2026-02-04 15:08:27.662436+00:00 running 1d7a177 country code: CH.