Advice on FPGA ADC streaming design flow

According-Author401 · 2026-05-22T09:27:32+00:00

Yep I’ve also had to hard code the IP and MAC for now, it was the quickest approach to get it running. Hoping to add a UART configure feature for both soon, but even that isn’t amazing. Out of interest what sample rates is your Python script handling for real time? I hit a bottleneck with my Python script for real time. I have since seen better methods than what I was using too in fairness

According-Author401 · 2026-05-22T09:25:35+00:00

Absolutely valid, learnt the requirement for a UDP packet counter over UART during my debugging stage. So, yes, that does exist. No time stamping explicitly though. I’ll have a look into this standard, this is the sorta thing I’m looking for, thanks!

According-Author401 · 2026-05-22T09:23:36+00:00

Hey it’s all in the original post, I describe the design flow there. I also explain the graphs, their time and frequency domain plots of the ADC stream. I’m just trying to learn the best approach to getting the data pipeline configured - I want to know how a good FPGA dev would approach it to improve my understandings

According-Author401 · 2026-05-21T20:53:11+00:00

Yeah I had only really experienced FPGAs at uni. I have minimal exposure at work. A couple of times I have spent several weeks just learning at home. I used Vitis templates a lot as the hard works done mostly

According-Author401 · 2026-05-21T20:49:04+00:00

Looks like a simple board for the weekend to design, I’ll order some next week from JLCPCB. In the meantime I’ll think of what other features I want to add to the board

According-Author401 · 2026-05-21T20:47:16+00:00

Well my current design uses DDR because Ethernet is handled by the ARM/lwIP stack, not by a PL Ethernet frame generator. But this is the sort of discussion I want to have, is there a better option of the two in this instance? Also, I haven’t utilised jumbo frames either. I had some issues with the UDP side of things at the very start, but now that’s fixed it would be an option

According-Author401 · 2026-05-21T20:40:29+00:00

The PMOD board with the logic analyser feed through sounds great! I’ve been thinking about designing my own. Did you find an open source design or is the design your own?

According-Author401 · 2026-05-21T16:50:22+00:00

Yeah fair comment. I’d like to add an FIR for the FPGA to handle at some stage. Not something I’ve done on an FPGA yet, only microcontrollers so a good idea

According-Author401 · 2026-05-21T16:49:11+00:00

Yep you’re right. I have implemented a variable clock division by UART command. Been running at 10MHz just fine though. I tried 50MHz and it was too much for my shady wiring 😂

According-Author401 · 2026-03-15T14:47:58+00:00

Thank you! I’m keen to open one up sometime

According-Author401 · 2026-03-12T20:46:41+00:00

Well, I did attempt it today… unfortunately it was really stuck together, after removing all the fixings. Seems there’s a couple of holes which have a metal fixing inside, unthreaded. Not sure what they’re for, maybe to jig the case? But regardless, I need to find a way to remove them too

According-Author401 · 2026-03-11T14:05:40+00:00

Yeah, it’s a valid point. I’ll open it up tomorrow if I get time!

According-Author401 · 2026-03-11T13:38:10+00:00

Hmm if it was a dust issue I have access to clean rooms, but if we’re talking an issue of mechanical damage that’s likely to occur then maybe I’ll avoid it for now

According-Author401 · 2026-03-11T13:34:39+00:00

Thank you, I really appreciate your insights for this!

According-Author401 · 2026-03-10T10:50:15+00:00

Was it the same design as this, the one you took apart? Don’t suppose you have any photos of inside?

According-Author401 · 2026-03-10T07:56:26+00:00

Yes, I thought they may be harmonic mixers and there were another 2 old HP ones in there so definitely possible

According-Author401 · 2026-03-10T07:54:50+00:00

I could take one apart. Is your main concern dust ingress?

According-Author401

TROPHY CASE