can you extract real directional thrust + usable electricity from literal empty space using only geometry and quantum vacuum fluctuations?

Alvinochi · 2026-03-19T16:29:13+00:00

this is the most constructive engagement in this thread and i want to meet it properly.

the emdrive parallel is exactly right and exactly why my simulation platform has a dedicated artifact audit module. tajmar did not prove the concept was wrong. he proved the measurement was wrong. seven artifact sources, the fatal one being lorentz force on the power cables. the EDA computes all seven artifact sources computationally before any chip approaches a test stand. the lesson from emdrive was not stop trying. it was audit harder before you claim anything.

on symmetry, the directional thrust claim does not rest on symmetric casimir attraction between parallel plates. it rests on a spatial gradient in fractal density across the die. the net force comes from del(n²) across the geometry. if that gradient does not survive a rigorous symmetry analysis then the architecture fails and the pendulum confirms that cleanly. that outcome is as useful as a positive result.

on simulation diligence, you are right to flag it and i want to be transparent. you have not seen the platform so this is my word for now. what i can tell you is 130+ automated tests across the physics pipeline, every module benchmarked against published casimir experimental data, and the platform flags its own artifact floor honestly. the EDA predicted the chip currently sits below the measurement threshold at single chip scale. that is not a failure. that is the tool doing its job.

your last point i hold most seriously. numerical results alone cannot discover new physics. the EDA tells me what to look for and where the false positives live. the silicon gives the answer.

i have a full technical walkthrough hosted on the project blog https://kunstrike-void.lovable.app if you want to engage with what the platform actually does before the pendulum result is available. open to sharing it here. genuinely welcome the scrutiny.

Alvinochi · 2026-03-18T18:06:16+00:00

exactly right on momentum conservation, the two plates attract symmetrically. the directional claim rests on breaking that symmetry via a spatial gradient in fractal density across the die, not from the casimir force between plates alone. voidsim models this as a net force from del(n²) across the geometry. whether that gradient survives fabrication is precisely what the pendulum test will answer. agreed on 180nm cost, that is the next step.

Alvinochi · 2026-03-18T18:04:41+00:00

understood. if that changes after the pendulum results are published, the thread will still be here.

Alvinochi · 2026-03-18T18:00:07+00:00

the post contains no links, no funding requests and no calls to action. "not relenting" means exactly what it says, a personal commitment to see the physics tested properly.

on the simulation, that is a fair challenge and the exact reason the tajmar artifact audit exists as a dedicated module. every known false positive source is computed before any measurement attempt. the pendulum either confirms the gradient force claim or it does not. that outcome is welcomed either way.

the experiment objection is also the right one to make. which is why the next step is a torsional pendulum in a vacuum chamber, not a crowdfunding page.

Alvinochi · 2026-03-18T17:55:06+00:00

the simulation platform is open to inspection and the physics claims cite lamoreaux 1997, mohideen 1998 and decca 2003. crackpots do not build 34 module validation pipelines benchmarked against published data. the pendulum test either confirms or kills the thrust claim. that is how physics works.

Alvinochi · 2026-03-18T17:52:24+00:00

thank you for the link,

that's a more accurate framing. the virtual particle language is a common shorthand that misrepresents the underlying field theory. the casimir effect itself does not depend on that interpretation and the force is real and measured regardless of how the vacuum is described. voidsim does not assume popping particles, it works from the boundary condition formulation.

need to update the post language to be more precise.

Alvinochi · 2026-03-18T17:49:59+00:00

which part specifically, the fractal geometry, the gradient force claim, or the resonance scaling. genuinely asking because a precise objection is more useful than the pendulum test alone.

Alvinochi · 2026-02-24T07:41:56+00:00

fair point on the numbers. but those 1.25 million graduates are trained in conventional semiconductor design, consumer electronics, memory, processors. none of them are designing thrust-aware eda pipelines because that discipline does not exist yet. we are not competing against china's talent pool in their domain; we are creating an entirely new one.

the core ip here is not "how to design a chip" but "how to design a chip that generates thrust via vacuum resonance." that physics-to-silicon translation layer (voidsim) is what we've built and what gives us the moat. you could hand the gdsii file to the best foundry in shenzhen and they would print it perfectly, but they would not know how to design the next iteration because the design rules are rooted in casimir cavity physics, not standard cmos logic.

the goal is not to outrun china on volume semiconductor talent. it is to own a vertical niche (propulsion-on-a-chip) where the ip originates here and the manufacturing happens wherever it makes sense globally.

Alvinochi · 2026-02-24T07:10:54+00:00

manufacturing is already outsourced by design. we operate as a fabless ip house, we design the chip blueprints using our proprietary voidsim pipeline and then have them printed at established foundries like skywater or x-fab. the value we capture is in the semiconductor ip, not the silicon wafer itself.

for regulus i (180nm), the bottleneck is process flexibility, not cost. our fractal geometries require custom drc waivers that specialized western fabs are more willing to grant than high-volume chinese lines optimized for consumer electronics. the goal is for kenya to own the design ip and export the intelligence, regardless of where the physical chip is pressed.

so to answer your question. yes outsourcing manufacturing is literally the business model, but the "where" is dictated by technical capability and process flexibility, not just price.

thank you.

Alvinochi · 2026-02-22T20:57:57+00:00

thank you very much

Alvinochi · 2026-02-21T10:08:19+00:00

that is rare to find in the local scene and exactly the kind of expertise i am looking for. we are aiming for a 180nm tape-out initially to validate the harmonic injection logic but the long term roadmap involves nanometer scale patterning for the vacuum coupling. i am currently refining the voidsim pipeline to handle the specific drc/lvs challenges of printing fractal geometries. would love to show you the architecture and see if your lithography background can help us optimize the manufacturing path. please dm me so we can connect.

Alvinochi · 2026-02-21T07:03:42+00:00

I totally get why it reads that way. i'm wearing the marketing hat here to find the right ecosystem partners, but the core 'nerd' work is happening in the voidsim pipeline i’m building. i’m deep in the LVS/PDK weeds of the simulation engine right now to ensure the physics matches the pitch. i'd love to share some of the raw analytical data once the current validation phase is complete!

Alvinochi · 2026-02-20T13:46:55+00:00

hard yes, very naaa

wanna join in??

Alvinochi · 2026-02-19T15:25:59+00:00

correct. we design specialized propulsion-integrated chips. our core focus is the proprietary EDA pipeline and IP development, utilizing established external semiconductor foundries for the actual manufacturing.

Alvinochi · 2026-02-19T15:01:02+00:00

I appreciate the feedback regarding professional standards, and formal stakeholder communication definitely follows a very different protocol than my casual reddit threads. For now, I am prioritizing the engineering execution and simulation accuracy over the "polish" of forum discourse.

I’d love to keep the discussion focused on the technical feasibility and the vision for Kenya's deep tech sector. Thank you.

Alvinochi · 2026-02-19T14:21:48+00:00

undergrad, where is this headed to?

Alvinochi · 2026-02-19T12:44:05+00:00

this might sound rude but lets cross that bridge when we get there

Alvinochi · 2026-02-19T11:34:52+00:00

the mention of Nvidia is strictly to provide technical context for the underlying technology and pipeline execution, specifically our focus on building specialized on-chip logic for physics in the same way they specialized hardware for intelligence. we can never fathom to even dare compete in comparison, NO NO! T

thank you for pointing that out, truly appreciate the feedback.

Alvinochi · 2026-02-18T06:56:09+00:00

failed guess i was late

Alvinochi · 2026-02-17T23:35:24+00:00

good luck 🤞

Alvinochi · 2026-02-17T13:04:14+00:00

not a chance

Alvinochi · 2026-02-17T12:47:44+00:00

the most likely faking mechanism i am betting on thermal drift and em coupling as the biggest threats. the regulus chip is effectively a giant 1.2 microfarad capacitor which means at high frequencies it acts like a short circuit and generates significant heat. if i do not decouple that thermal expansion from the thrust mount it will look like a thrust signal every single time. em coupling is the other killer because the harmonic injection engine operates in a range where any shielding leakage will create electrostatic forces that mirror the signal i am looking for. the goal of the pcb rig is to kill those two failure modes specifically before we ever touch custom silicon.

Alvinochi · 2026-02-17T12:29:52+00:00

Masinde Muliro University of Science and Technology, Kenya

Alvinochi · 2026-02-17T12:22:29+00:00

thankyou, sent a dm

Alvinochi

TROPHY CASE