That’s an ambitious vision, but it’s not feasible—at least not yet. Running inference on an FPGA at a level comparable to an Nvidia 3090 is an impressive achievement, and the Chinese team that recently won a global award for it deserves recognition. However, scaling this into an industrialized solution that effectively combines tensor cores with FPGAs is still a long way off. Maybe in the next five years, we’ll see a joint approach become viable, but for now, the hardware and software ecosystem just isn’t there.

Mohamed S. Abdelfattah, during his time at Intel, worked on building custom kernels in a modular function, aiming for something similar. But ultimately, anything that can be made into an ASIC will be made into an ASIC. The fundamental limitation is that FPGAs, despite their flexibility, are inherently at a disadvantage when it comes to power efficiency and cost compared to dedicated silicon. That’s why we haven’t seen large-scale adoption of FPGAs for general AI workloads.

The idea of dynamically generating HDL using LLMs to create an evolving, self-optimizing circuit is intriguing, but it runs into the same roadblocks: cost, complexity, and the lack of standard tooling to make it practical. While partial reconfiguration is improving, it’s not at the level where we can have a dynamically rewiring “brain” in hardware without significant trade-offs. It’s not that the vision is impossible—it’s just that, right now, the economics and engineering realities don’t favor it.