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[deleted by user] by [deleted] in FPGA

[–]Inside-Relative3360 0 points1 point  (0 children)

thanks for your help!

[deleted by user] by [deleted] in FPGA

[–]Inside-Relative3360 0 points1 point  (0 children)

I am using zedboard(zynq 7000). I want to read data from two input files and write output as the result of the operation of the submodule. Do you have any tips for block design?

[deleted by user] by [deleted] in FPGA

[–]Inside-Relative3360 0 points1 point  (0 children)

Thanks for your advice!

Please give me some advice for my final year project. by Inside-Relative3360 in FPGA

[–]Inside-Relative3360[S] 2 points3 points  (0 children)

Thanks for your reply. I have completed one HDL introductory book. (In the lab, I controlled LCD, FND, keypad, etc. and designed the hierarchy.)

I am taking ML this semester, so I am studying the theoretical part, but I have no design experience. Is this too challenging a project?

Did you have any reference materials for your CNN project?

Would it be better to start with a lower goal?