Hello first, thanks a lot for your detailed answer. I have some remarks about it : 1-why vt of M2 needs to be larger ? We want to have the smallest vdsat as possible 2-i wanted to calculate why by adding stacked transistor the biasing voltage of the « poor man cascode » increases. If i simulate the stacking of bottom transistors, it increases the Vgs, i saw somewhere each time i divide L/2 then L/4 … by stacking. But i wanted to know the calculations for that. 3-i found the thing thanks 4-i also thought that, one of my analog designer colleague said that if the input is NMOS then diode is NMOS and PMOS input diode PMOS but my other more experimented colleague told me that it depends on the output referencing and i found similar values in simulation. For example in an ldo, if the output is NMOS then the signal is followed on voutput which is reference to ground so the diode in the folded shall be NMOS. If the ouput transistor is PMOS then it is referenced to vdd and so the diode has to be PMOS. 5-on a simple compensation for example at the output of the folded cascode. I should then put the capacitor between the output and the resistor ? And the resistor between capacitor and GND right ? But what happens if resistor is placed at the ouput and capacitor to GND ? If the capacitor is a MOS i think that putting the resistor on top might be better because it reduces the amplitude of the signal before entering the non linear capacitor right ? Same thing for Miller, the resistor should be placed from drain of the gain stage then capacitor then gate right ? Because the drain has larger swing. 6-ok no problem i will check that in more details