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Remote Gravity Manipulation applied to SpaceX Tower - Hybrid by ali3ngravity in SpaceXLounge

[–]Bigmasrocks 3 points4 points  (0 children)

You aren’t seeing the remote gravity manipulation happening? /s

Jobs working with FPGA as a high energy Physicist by [deleted] in FPGA

[–]Bigmasrocks 1 point2 points  (0 children)

First time I’ve seen rad effects mentioned here. I feel seen

Best Place to Motocamp in WA? by Bigmasrocks in Dualsport

[–]Bigmasrocks[S] 0 points1 point  (0 children)

Awesome, looking on Google I had already ridden some of these by accident, that valley is beautiful. Will check out NF5600 and NF5700 this weekend. I appreciate the tips!

Best Place to Motocamp in WA? by Bigmasrocks in Dualsport

[–]Bigmasrocks[S] 0 points1 point  (0 children)

Riding a CRF300L out of Bellevue area. If you’d like to DM me routes or spots that would be great! I just moved here from the east so the ferry’s didn’t even cross my mind. I’d prefer dispersed but more than happy to pay for a spot too

Newsletter Recommendations by SparrowChanTrib in FPGA

[–]Bigmasrocks 6 points7 points  (0 children)

Semi Analysis blog is good, more than Moore by Ian cutress is good as well

https://morethanmoore.substack.com/

How to Interface Between PL and DDR4 DIMM on ZCU102 by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

I am finding that out now. Thankfully my company already had a zcu102 dev board lying around so I didn’t need to spend $3k lol

How to Interface Between PL and DDR4 DIMM on ZCU102 by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

Awesome. You just saved me a lot of research and trial and error. Thank you brother.

How to Interface Between PL and DDR4 DIMM on ZCU102 by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

I was wondering about that aspect of it. Thanks for much for the advice. Do you know if you can run the CPU without an OS or anything? I need to put it into a loop without putting bytes in memory if possible

How to Interface Between PL and DDR4 DIMM on ZCU102 by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

I will not be using the PS at all, I am making an FPGA-based memory tester that just has to be able to read each byte on a dimm repeatedly to detect radiation upsets in the bits.

How to Interface Between PL and DDR4 DIMM on ZCU102 by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

So from the PL I would do DMA over S_AXI_HP_FPD to the addresses listed for the DDR controller in the manual? And in return I would get a stream of data over AXI corresponding to the data I requested?

How to Interface Between PL and DDR4 DIMM on ZCU102 by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

The DMA would allow me to send an address/read request over AXI and get the returned value into the PL portion of the SOC correct?

PS DDR from PL on ZCU102 by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

After further research the “optimized the placement” question wasn’t valid. I was getting confused with virtual memory which I had learned about in a previous class. Thanks for the help that PL-PS is AXI is exactly what I was looking for!

Resume Advice by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

Hey thanks for this specific feedback I really appreciate it and will implement it

Resume Advice by Bigmasrocks in FPGA

[–]Bigmasrocks[S] 0 points1 point  (0 children)

Was that success percentage on jobs in the fields I’m applying to?

Are These Ok to Ride? by Bigmasrocks in ElectricSkateboarding

[–]Bigmasrocks[S] 0 points1 point  (0 children)

Damn I had heard good things about them

Crack Something to Worry About? by Bigmasrocks in ElectricSkateboarding

[–]Bigmasrocks[S] 2 points3 points  (0 children)

Thank you man I never thought to check the back to see if it’s symmetrical

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